First Picture of a Cell Processor - Smaller Than a Pushpin, More Powerful Than a PC

[Bill Todd]

Uh, released in 2003, not 1998.

There were no substantial changes in the core (IIRC they got to enlarge
the victim buffer, and that was about it). They weren't even allowed to
tweak things to make use of faster on-chip L2 cache.

EV7 essentially uses a core implementation, not just design, that
shipped in 1998.

e a case that the Pentium-M is a 1992 core
'Fraid not.

- bill

 

[myren, lord]

I don't want to hype today *too* much, for fear of disappointment. but in
less than 10 hours, there is *supposed* to be quiet a bit of information
released on the Cell Processor Element, Cell APU and Cell PU. the basic
building blocks of Cell Processors and Cell Systems. As well as information
on the software side, if i'm not mistaken.

I havent found much new information on Cell since the Sony regalia.
Most of it was available months ago from the net, and often with more in
depth analysis and less fanfare. The coverage has been flat out spotty,
hell, The Register went straight off the deep end; I think we should at
least wait for the video game system to come out to let us get some idea
what Cell can do before we decide its going to singlehandedly jump start
the ubiquotous grid, gain sentience and take over the world.

They'd better have one badass API to program this thing.

Oh, and this cross posting shit is getting excessive.

Regards,
Myren

 

[daytripper]

I've wondered the very same thing myself. To me, from the outside at
least, it seems like it would make sense. Rambus memory has been used
in video cards before, but only in some very rare situations. I don't
even think there would be much of a cost difference for the memory
chips even, given that video cards use very high-end/high speed GDDR3
memory, quite a bit more expensive than the DDR memory used in desktop
PCs.

However nVidia has commented before that they have evaluated Rambus
memory on more than one occasion and found it to be unsuitable for
their application. It's always made me wonder if maybe they know
something that the rest of us don't? Or maybe their decision was only
partly based on technical reasons and partly on more political/legal
related ones? Or maybe it has to do with Rambus licensing fees for
the memory controller rather than for the memory itself?

In short, I really don't know what the answer is here.


Not much from where I'm standing.

Some times you get beau coup pins for "free". Like when you need a humongous
die and package to fit all the functional bells, whistles and go-fasters on
the chip...

/daytripper

 

[James Boswell]

On 2005-02-10 01:07:53 -0500, "NEXT BOX" <[email protected]> said:

http://macdailynews.com/index.php/weblog/comments/4967/

Intel has no answer to the 'Cell' processor; will Apple use
it in Macs?


Not too likely. The cell is not a general purpose CPU; Most programs
have a working set larger than the 256k memory the Cell supports,
and changing them to work in 256k increments would rather hard.

The Cell seems to be intended for use as a sort of co-processor, and
maybe they could be used to build a sort of GPU. But the benefits
will be in any event pretty limited.

not -

the cell is a G5 processor with *ADDTIONALLY* cpus on the same chip

also if you had bothered to read -
the cell's G5 carries a 32K level cache, and a 512K level 2 cache
while the 'satellite' cpus carry the 256K cache

excepting die size (giant at 221 mm) there is no practical reason
that these could not be put into Macs, or any other general use PC
(including in a dual [Mac tower] or quad [IBM Server] processor
configuration).

Cell's master CPU is not a G5 processor. it's much more streamlined
than a G5.

To be fair, if Apple were to use it, they'd probably call it a G5

it's NOT a 970 series chip though, it's a 64bit PPC+VMX core, with 2-way
multithreading.. but it bears little resembalance to recent Power cores..
looks more like an IBM research project from a few years ago called Rivina
if anything... short pipeline + high clock.

-JB

 

[keith]

I havent found much new information on Cell since the Sony regalia.

Did you really expect to? This is ISSCC, not an architecture forum.

 

[keith]

Some times you get beau coup pins for "free". Like when you need a humongous
die and package to fit all the functional bells, whistles and go-fasters on
the chip...

....and sometimes faster pins are not so attractive. Sometimes those pins
are better used for power/ground.

 

[Mattinglyfan]

Soni tempori elseu romani yeof helsforo nisson ol sefini ill des Fri, 11
Feb
2005 16:52:21 +0000 (UTC), sefini jorgo geanyet des mani yeof do
uk.games.video.playstation, yawatina tan reek esk David Wang

[The rest of my article snipped]

Dear "NEXT BOX",

You managed to copy everything except the following copyright
statement. You are expressly forbidden to do what you did. Please
cease and desist. I will be contacting your ISP shortly.

Thank you for your attention to this matter.

You will have a small army of supporters, Mr Wang. May I suggest you take
it
further than just contacting his ISP? You'd be doing the whole of Usenet
a
great service if you got him banged up for this

Here here! Even though I doubt that it is from the real author.

deKay
--
+ Lofi Gaming - www.lofi-gaming.org.uk [Gamertag: deKay 01]
|- Gaming Diary - www.lofi-gaming.org.uk/diary/
|- My computer runs at 3.5MHz and I'm proud of that
|- Hurry up and go touch it.

 

[Alex Colvin]

http://www.intel.com/design/network/products/npfamily/docs/ixp2800_docs.htm#Datasheets

Similar concept. Very different purpose. The ixp2800 uses an ARM core
with no FPU where-as the Cell uses a POWER core with the full
instruction set and all the necessary execution units. The ixp2800
microengines are specialized units for data transfer, they move things
around, while the Cell coprocessors are specialized unis for FP vector

right. my thought was that a stripped-down embedded processor with a pile
of attached processors is not something new, and is not necessarily going
to change the face of computing.

also, the intel network processor is not amenable to programming in C,

 

[George Macdonald]

Soni tempori elseu romani yeof helsforo nisson ol sefini ill des Fri, 11
Feb
2005 16:52:21 +0000 (UTC), sefini jorgo geanyet des mani yeof do
uk.games.video.playstation, yawatina tan reek esk David Wang

[The rest of my article snipped]

Dear "NEXT BOX",

You managed to copy everything except the following copyright
statement. You are expressly forbidden to do what you did. Please
cease and desist. I will be contacting your ISP shortly.

Thank you for your attention to this matter.

You will have a small army of supporters, Mr Wang. May I suggest you take
it
further than just contacting his ISP? You'd be doing the whole of Usenet
a
great service if you got him banged up for this

Here here! Even though I doubt that it is from the real author.

You don't think the msg posted from Dave Wang is from the real author of
the original articles? I can assure you it is. Go get 'im Dave!

 

[The little lost angel]

Here here! Even though I doubt that it is from the real author.

I'm pretty sure, even without checking the site I suspect it's posted
on, that Mr Wang is the author. He's the "real world" author of more
than a handful of technical articles AFAIK.

--
L.Angel: I'm looking for web design work.
If you need basic to med complexity webpages at affordable rates, email me
Standard HTML, SHTML, MySQL + PHP or ASP, Javascript.
If you really want, FrontPage & DreamWeaver too.
But keep in mind you pay extra bandwidth for their bloated code

 

[Tony Hill]

Tony Hill wrote:

...


Yeah - really pathetic performance from a 1998 core two full process
generations out of date.

Uhh, yeah. That's why I wrote in the VERY next line of the message:

"Now again those results are not necessarily an indication that Rambus
is a failure because there are MANY other issues holding the EV7s
performance back (only some of which are technical)."


Besides, the Opteron uses largely the same core as the original
Athlon, released in 1999. It might have a few more changes than for
the EV6 vs. EV7, but as is the case with the Alphas the primary
differences between Athlon and Opteron are in I/O and the memory
subsystem.

 

[Tony Hill]

Some times you get beau coup pins for "free". Like when you need a humongous
die and package to fit all the functional bells, whistles and go-fasters on
the chip...

True, but in an application with a virtually limitless appetite for
bandwidth, like a modern GPU, it still seems to me like getting the
most bandwidth/pin would be attractive. Just look at the memory chips
that they ARE using on top-end GPUs, GDDR3 memory running at 500MHz+!
That stuff does not come cheap, so obviously they've got a reason to
use them.

 

[daytripper]

True, but in an application with a virtually limitless appetite for
bandwidth, like a modern GPU, it still seems to me like getting the
most bandwidth/pin would be attractive. Just look at the memory chips
that they ARE using on top-end GPUs, GDDR3 memory running at 500MHz+!
That stuff does not come cheap, so obviously they've got a reason to
use them.

If there was an advantage to be had for a GPU to use something other than
GDDR3 you can be sure someone would be using it...

 

[Jeremy Williamson]

Did you really expect to? This is ISSCC, not an architecture forum.

Just back from HPCA, which had a Cell presentation and no new info. Most of
the slides were just repetitions of the ISSCC presentation. Microprocessor
Report looks to have a nice summary of what's know so far. Haven't finished
reading it yet though...

Jeremy

 

[keith]

Just back from HPCA, which had a Cell presentation and no new info. Most of
the slides were just repetitions of the ISSCC presentation. Microprocessor
Report looks to have a nice summary of what's know so far. Haven't finished
reading it yet though...

There's a lot more hype to wade through before you're going to have the
answers you want. They've not discussed the details of the architecture
yet. My educated guess is that there will be another hype-dump at the
Microprocessor Forum in October.

Some may even be surprised. ;-)

 

[David Wang]

Just back from HPCA, which had a Cell presentation and no new info. Most of
the slides were just repetitions of the ISSCC presentation. Microprocessor
Report looks to have a nice summary of what's know so far. Haven't finished
reading it yet though...

I was hoping to talk to Peter Hofstee on the boat trip, but the whole panel
went out to dinner instead of the boat trip.

The 2 way glueless SMP thing was new, and a few more sentences were new
to me, but you're quite right, there were little that was "truly new" in
terms of stuff that wasn't talked about at ISSCC.

I am still trying to figure out whether the "64 TFlop rack" that Peter
talked about was a prototype rack filled with CELL processors, or was it
part of the generic challenges of architecture going forward, and the
rack could be anything, perhaps Bluegene L rather than CELL.

 

[Jeremy Williamson]

There's a lot more hype to wade through before you're going to have the
answers you want. They've not discussed the details of the architecture
yet. My educated guess is that there will be another hype-dump at the
Microprocessor Forum in October.

Some may even be surprised. ;-)

E3 will be before that.

Jeremy

 

[Jeremy Williamson]

I was hoping to talk to Peter Hofstee on the boat trip, but the whole panel
went out to dinner instead of the boat trip.

The 2 way glueless SMP thing was new, and a few more sentences were new
to me, but you're quite right, there were little that was "truly new" in
terms of stuff that wasn't talked about at ISSCC.

I am still trying to figure out whether the "64 TFlop rack" that Peter
talked about was a prototype rack filled with CELL processors, or was it
part of the generic challenges of architecture going forward, and the
rack could be anything, perhaps Bluegene L rather than CELL.

Would you want to be on a boat in that weather? Wonder if I can get a
partial refund... hmmm...

2 way glueless SMP? Ehhh... Which version of the SMP acronym are we using?
Cell is definitly not a shared memory processor. Ok, ok, sorry I'm just
bitching about reuse of basic acronyms. Yes, I know its for symmetric
multiprocessing... I'd expect them to be glueless or the whole Cell idea
would fall on it's behind.


64 TFlop rack? Don't recall that. Yeah, probably just a rack of CELLs...

I was in the back of the room so couldn't hear him all that well. Not
exactly a great public speaker... of course, that's not what they pay him
for...

Jeremy

 

[David Wang]

Would you want to be on a boat in that weather? Wonder if I can get a
partial refund... hmmm...

It wasn't about the boat trip.

You have a bunch of senior architects trapped on a boat of 3 hours. You have
3 hours to sell them on your insane ideas, and they have nowhere to run.
(Some of the big names didn't show up though)

My friends and I were joking that if the boat was to have sunk, it would
set back the field of computer architecture for a few years.

2 way glueless SMP? Ehhh... Which version of the SMP acronym are we using?
Cell is definitly not a shared memory processor. Ok, ok, sorry I'm just
bitching about reuse of basic acronyms. Yes, I know its for symmetric
multiprocessing... I'd expect them to be glueless or the whole Cell idea
would fall on it's behind.

Well, Peter showed that you can do 2 way glueless and also showed that
you can do more than 2 ay with a switch. I asked him if he could do a
glueless ring, and he said no, it has to be a coherent switch for N > 2.

64 TFlop rack? Don't recall that. Yeah, probably just a rack of CELLs...

Everyone else thinks that it was just a Blue Gene rack. I thought it
was CELL based.

I was in the back of the room so couldn't hear him all that well. Not
exactly a great public speaker... of course, that's not what they pay him
for...

Yes, the variable-distance-between-mouth-and-microphone issue in
conjunction with the variable speed in flipping through the slides
and some mumbling made the talk hard to follow.

I was thinking that I should have pulled the Japanese Journalist
trick and just started taking pictures of the slides.