M
Mike Tomlinson
NEXT BOX said:
Oh well. I won't be buying anything containing a Cell processor then.
First Picture of a Cell Processor - Smaller Than a Pushpin, More Powerful Than a PC
Oh well. I won't be buying anything containing a Cell processor then.
G
Gnu_Raiz
For a minute I thought I was in an Alt.binaries group, you know who can
post first about the cell processor. Kind of like all geeks, falling all
over themselves to get the news out, between this and Star Trek being
canceled, guess its got everyone worked up.
Gnu_Raiz
G
Gnu_Raiz
I have to agree with you on that, seems that Sony is playing a Microsoft
with the next console.
I am surprised that no one has posted this link to a brief overview of the
chip.
http://arstechnica.com/articles/paedia/cpu/cell-1.ars
I wonder how Intel will respond to this new development, seems like a
shift might be comming. Of course we all know that development, and market
share has nothing to do with anything, probably going to be the same old
same old.
Gnu_Raiz
T
Toon Moene
Tony said:
Well, there's this much-hoped-for option: Enhance Intelligence Level.
As someone put it: "There's this `brightness' knob, but it doesn't seem
to have the right effect".
OK, 1/2
[ Who needs television, when you have the Internet ? ]
D
Douglas Siebert
Tony Hill said:
That assumes it runs at 100% all the time. Are there any games today
that max out a PS2, Xbox, or a high end PC GPU for more than a few seconds
at a time? I'm sure there are complex sequences where you hit the max
but it isn't as though you have that kind of complexity all the time.
Plus, this is at 90nm, and unless they are planning to ship the PS3 in
time for this xmas, it'll be built on 65nm and the power needs would be
reduced.
I don't see that cost as a problem for putting them in PS3 or HDTVs. And
you can cut that size pretty much in half for 65nm which will be where the
bulk of Cells are made, and it'll really be cheap later in life as a 45nm
product.
You are assuming that they don't use multi channel memory chips. No reason
they can't make a single 1Gb XDR chip that has 3 or 4 XDR interfaces with
independant memory arrays, and use two if they wanted 256MB which would
probably be a reasonable target.
For everything else, when they will be selling PS3s in the tens of millions,
perhaps as many as a hundred million over its lifetime, economies of scale
can make a lot of things cheap that wouldn't be on say a PC motherboard,
most of which are probably lucky to sell 100K units considering their short
lifetime and field filled with many nearly identical competitors.
J
Jeremy Williamson
Mike Tomlinson said:
PS2 used Rambus as well... it actually works decently in their HW config.
J
K
keith
On Mon, 07 Feb 2005 23:12:35 -0600, NEXT BOX wrote:
Idiot! Don't you have any input of your own? Must you spam the groups
with other's words?
Idiot! Don't you have any input of your own? Must you spam the groups
with other's words?
N
NEXT BOX
http://arstechnica.com/articles/paedia/cpu/cell-2.ars
Introducing the IBM/Sony/Toshiba Cell Processor -- Part II: The Cell
Architecture
By Jon "Hannibal" Stokes
In today's session, IBM introduced the overall architecture of the Cell
processor. Unfortunately, they didn't include many more microarchitectural
details in today's session than they did in yesterday's. Most of the session
covered issues like power management, clocking, the design process, and so
on. So today's article is going to be more along the lines of a follow-up to
yesterday's piece. I'll fill in the new information that I've picked up, as
well as clarifying leftover questions from yesterday.
The Cell's basic architecture
The basic architecture of the Cell is described by IBM as a "system on a
chip" (SoC) design. This is a perfectly good characterization, but I'd take
it even further and call Cell a "network on a chip." As I described
yesterday, the Cell's eight SPUs are essentially full-blown vector
"computers," insofar as they are fairly simple CPUs with their own local
storage.
These small vector computers are connected to each other and to the 512KB L2
cache via a element interface bus (EIB) that consists of four sixteen-byte
data rings with 64-bit tags. This bus can transfer 96 bytes/cycle, and can
handle over 100 outstanding requests.
The individual SPEs can use this bus to communicate with each other, and
this includes the transfer of data in between SPEs acting as peers on the
network. The SPEs also communicate with the L2 cache, with main memory (via
the MIC), and with the rest of the system (via the BIC). The onboard memory
interface controller (MIC) supports the new Rambus XDR memory standard, and
the BIC (which I think stands for "bus interface controller" but I'm not
100% sure) has a coherent interface for SMP and a non-coherent interface for
I/O.
Unfortunately, today's session was severly lacking in information on the
64-bit PPC core that handles the Cell's general-purpose computing chores. We
do know that this core has a VMX/Altivec unit, at least one FPU, and
supports simultaneous multithreading (SMT). It's also in-order issue, like
the SPUs. So it appears that this core also lacks an instruction window,
presumably for the same reasons that the SPUs do (i.e. to save on die space
and cut down on control logic.) I have in my notes that the core is
two-issue, like the SPUs, but I can't find this corroborated anywhere else.
So it's possible that the core only issues two instructions per cycle peak,
i.e. one from each currently-running thread. I'd imagine that if this is the
case, this core's pipeline is very short. This would fit with the SPUs, in
which the pipeline was also kept short and simple.
The entire Cell is produced on a 90nm SOI process with 8 layers of copper
interconnect. The Cell sports 234 million transistors, and its die size is
221mm2. (This is roughly the size of the Emotion Engine at its
introduction.) The PPC core's 32KB L1 cache is connected to the system L2
cache via a bus that can transfer 32 bytes/cycle between the two caches.
The Cell and Apple
Finally, before signing off, I should clarify my earlier remarks to the
effect that I don't think that Apple will use this CPU. I originally based
this assessment on the fact that I knew that the SPUs would not use
VMX/Altivec. However, the PPC core does have a VMX unit. Nonetheless, I
expect this VMX to be very simple, and roughly comparable to the Altivec
unit o the first G4. Everything on this processor is stripped down to the
bare minimum, so don't expect a ton of VMX performance out of it, and
definitely not anything comparable to the G5. Furthermore, any Altivec code
written for the new G4 or G5 would have to be completely reoptimized due to
inorder nature of the PPC core's issue.
So the short answer is, Apple's use of this chip is within the realm of
concievability, but it's extremely unlikely in the short- and medium-term.
Apple is just too heavily invested in Altivec, and this processor is going
to be a relative weakling in that department. Sure, it'll pack a major SIMD
punch, but that will not be a double-precision Alitvec-type punch.
Introducing the IBM/Sony/Toshiba Cell Processor -- Part II: The Cell
Architecture
By Jon "Hannibal" Stokes
In today's session, IBM introduced the overall architecture of the Cell
processor. Unfortunately, they didn't include many more microarchitectural
details in today's session than they did in yesterday's. Most of the session
covered issues like power management, clocking, the design process, and so
on. So today's article is going to be more along the lines of a follow-up to
yesterday's piece. I'll fill in the new information that I've picked up, as
well as clarifying leftover questions from yesterday.
The Cell's basic architecture
The basic architecture of the Cell is described by IBM as a "system on a
chip" (SoC) design. This is a perfectly good characterization, but I'd take
it even further and call Cell a "network on a chip." As I described
yesterday, the Cell's eight SPUs are essentially full-blown vector
"computers," insofar as they are fairly simple CPUs with their own local
storage.
These small vector computers are connected to each other and to the 512KB L2
cache via a element interface bus (EIB) that consists of four sixteen-byte
data rings with 64-bit tags. This bus can transfer 96 bytes/cycle, and can
handle over 100 outstanding requests.
The individual SPEs can use this bus to communicate with each other, and
this includes the transfer of data in between SPEs acting as peers on the
network. The SPEs also communicate with the L2 cache, with main memory (via
the MIC), and with the rest of the system (via the BIC). The onboard memory
interface controller (MIC) supports the new Rambus XDR memory standard, and
the BIC (which I think stands for "bus interface controller" but I'm not
100% sure) has a coherent interface for SMP and a non-coherent interface for
I/O.
Unfortunately, today's session was severly lacking in information on the
64-bit PPC core that handles the Cell's general-purpose computing chores. We
do know that this core has a VMX/Altivec unit, at least one FPU, and
supports simultaneous multithreading (SMT). It's also in-order issue, like
the SPUs. So it appears that this core also lacks an instruction window,
presumably for the same reasons that the SPUs do (i.e. to save on die space
and cut down on control logic.) I have in my notes that the core is
two-issue, like the SPUs, but I can't find this corroborated anywhere else.
So it's possible that the core only issues two instructions per cycle peak,
i.e. one from each currently-running thread. I'd imagine that if this is the
case, this core's pipeline is very short. This would fit with the SPUs, in
which the pipeline was also kept short and simple.
The entire Cell is produced on a 90nm SOI process with 8 layers of copper
interconnect. The Cell sports 234 million transistors, and its die size is
221mm2. (This is roughly the size of the Emotion Engine at its
introduction.) The PPC core's 32KB L1 cache is connected to the system L2
cache via a bus that can transfer 32 bytes/cycle between the two caches.
The Cell and Apple
Finally, before signing off, I should clarify my earlier remarks to the
effect that I don't think that Apple will use this CPU. I originally based
this assessment on the fact that I knew that the SPUs would not use
VMX/Altivec. However, the PPC core does have a VMX unit. Nonetheless, I
expect this VMX to be very simple, and roughly comparable to the Altivec
unit o the first G4. Everything on this processor is stripped down to the
bare minimum, so don't expect a ton of VMX performance out of it, and
definitely not anything comparable to the G5. Furthermore, any Altivec code
written for the new G4 or G5 would have to be completely reoptimized due to
inorder nature of the PPC core's issue.
So the short answer is, Apple's use of this chip is within the realm of
concievability, but it's extremely unlikely in the short- and medium-term.
Apple is just too heavily invested in Altivec, and this processor is going
to be a relative weakling in that department. Sure, it'll pack a major SIMD
punch, but that will not be a double-precision Alitvec-type punch.
T
Tony Hill
It doesn't much matter, you need to design for maximum power draw
unless you want your system to shut down randomly. Well, actually I
suppose you could take the Intel route and use thermal throttling to
prevent maximum power draw from overloading a borderline cooling
solution, but I haven't heard of such a solution for the Cell.
I'm not sure that they will be reduced all that much. Leakage current
is going WAY up for the 65nm node. With over 200M transistors it's
going to be TOUGH to keep leakage in check.
At 65nm it should be cheaper to make, though I don't expect much
volume of 65nm chips until late 2006/early 2007. I know IBM and Intel
are both aiming for almost a year earlier, and maybe I'm just being a
cynic, but I don't think they're going to get volume out anywhere
close to on time.
That may be an option (I'll admit that I'm no expert on how XDR
channel can/do work), though it would still seem like those would be
fairly expensive chips.
I'm sure that Sony will make a push for it, I'm just not convinced
yet. I would expect that the console will first come being rather
expensive ($500+?) and might have some trouble selling. Economies of
scale only take you so far, eventually you've got to pay for
everything.
Note that there are also some rumors floating around that the PS3
might use multiple Cell processors, not just one. Now, I'm not taking
these rumors as fact by any means, but if they do turn out to be
accurate then it would push the cost up quite a bit higher.
T
Tony Hill
Despite my rather distaste for Rambus the company and recognizing that
their technology just doesn't fit into the PC realm, for the PS2 and
the PS3 their stuff makes VERY good sense.
With the way that the PS2 processor and this new Cell processor work,
combined with the nature of the machine (ie to play games), bandwidth
is likely to be quite important while latency will be somewhat less
so. Remember that these processors are going to be doing a lot of
work traditionally associated with GPUs in a PC. Rambus' solutions,
both XDR now and RDRAM back when the PS2 was new, do offer VERY high
per-pin bandwidth and that's just the sort of thing that these
consoles need. The processors also have integrated memory controllers
which helps avoid some of the potential issues with Rambus in PCs. To
top it off, the memory chips are getting soldered right onto the
system board rather than hanging off multidrop sockets on the system
board.
Basically a PC and the PS2/PS3 have rather different designs and
different requirements. Hmm.. different solutions for different
problems... whodda thunk it! :>
Q
Quolik the lowbrow
Tony Hill, <[email protected]>, the ramshackle, moon-splashed farm
boy, and dishonest grocer and dealer in bad spices, puked:
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
boy, and dishonest grocer and dealer in bad spices, puked:
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
C
chrisv
NEXT said:
X-Complaints-To: (e-mail address removed)
Done.
*PLONK*
F
FredK
Jeremy Williamson said:
The example of Rambus done right is the Alpha EV7
R
relic
jack said:
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
(e-mail address removed)
C
chrisv
jack said:
It's just a stupid troll with a random name generator, which it uses
to avoid kill-files.
I advise deleting unread any post from someone with a name that
resembles, in any way, "Quolik the lowbrow".
N
NEXT BOX
http://games.slashdot.org/comments.pl?sid=138810&cid=11616545
Top 7 Myths of the New Cell Processor:
by Modab (153378) on Wednesday February 09, @04:56AM (#11616545) There are
so many people saying dumb things about the Cell and the upcoming PS3, I
have to set some things straight. Here goes:
1.. The Cell is just a PowerPC with some extra vector processing.
Not quite. The Cell is 9 complete yet simple CPU's in one. Each handles
its own tasks with its own memory. Imagine 9 computers each with a really
fast network connection to the other 8. You could problably treat them as
extra vector processors, but you'd then miss out on a lot of potential
applications. For instance, the small processors can talk to each other
rather than work with the PowerPC at all.
2.. Sony will have to sell the PS3 at an incredible loss to make it
competitive.
Hardly. Sony is following the same game plan as they did with their
Emotion Engine in the PS2. Everyone thought that they were losing 1-200
bucks per machine at launch, but financial records have shown that besides
the initial R&D (the cost of which is hard to figure out), they were only
selling the PS2 at a small loss initially, and were breaking even by the end
of the first year. By fabbing their own units, they took a huge risk, but
they reaped huge benefits. Their risk and reward is roughly the same now as
it was then.
3.. Apple is going to use this processor in their new machine.
Doubtful. The problem is that though the main CPU is PowerPC-based like
current Apple chips, it is stripped down, and the Altivec support will be
much lower than in current G5s. Unoptomized, Apple code would run like a G4
on this hardware. They would have to commit to a lot of R&D for their OS to
use the additional 8 processors on the chip, and redesign all their tweaked
Altivec code. It would not be a simple port. A couple of years to complete,
at least.
4.. The parallel nature will make it impossible to program.
This is half-true. While it will be hard, most game logic will be
performed on the traditional PowerPC part of the Cell, and thus normal to
program. The difficult part will be concentrated in specific algorithms,
like a physics engine, or certain AI. The modular nature of this code will
mean that you could buy a physics engine already designed to fit into the
128k limitation of the subprocessor, and add the hooks into your code. Easy
as pie.
5.. The Cell will do the graphics processing, leaving only rasterezation
to the video card. Most likely false. The high-end video cards coming out
now can process the rendering chain as fast as the Cell can, looking at the
raw specs of 256Gflops from the Cell, as opposed to about 200GFlops from
video cards. In two years, video cards will be capable of much more, and
they are already optomized for this, where the Cell is not, so video cards
will perform closer to the theoretical limits.
6.. The OS will handle the 8 additional vector processors so the
programmer doesn't need to.
Bwahahaha! No way. This is a delicate bit of coding that is going to
need to be tweaked by highly-paid coders for every single game. Letting on
OS predictively determine what code needs to get sent to what processor to
run is insane in this case. The cost of switching out instructions is going
to be very high, so any switch will need to be carefully considered by the
designer, or the frame-rate will hit rock-bottom.
7.. The Cell chip is too large to fab efficiently.
This is one myth that could be correct. The Cell is huge (relatively),
and given IBM's problems in the recent past with making large, fast PowerPC
chips, it's a huge gamble on the part of all parties involved that they can
fab enough of these things.
Top 7 Myths of the New Cell Processor:
by Modab (153378) on Wednesday February 09, @04:56AM (#11616545) There are
so many people saying dumb things about the Cell and the upcoming PS3, I
have to set some things straight. Here goes:
1.. The Cell is just a PowerPC with some extra vector processing.
Not quite. The Cell is 9 complete yet simple CPU's in one. Each handles
its own tasks with its own memory. Imagine 9 computers each with a really
fast network connection to the other 8. You could problably treat them as
extra vector processors, but you'd then miss out on a lot of potential
applications. For instance, the small processors can talk to each other
rather than work with the PowerPC at all.
2.. Sony will have to sell the PS3 at an incredible loss to make it
competitive.
Hardly. Sony is following the same game plan as they did with their
Emotion Engine in the PS2. Everyone thought that they were losing 1-200
bucks per machine at launch, but financial records have shown that besides
the initial R&D (the cost of which is hard to figure out), they were only
selling the PS2 at a small loss initially, and were breaking even by the end
of the first year. By fabbing their own units, they took a huge risk, but
they reaped huge benefits. Their risk and reward is roughly the same now as
it was then.
3.. Apple is going to use this processor in their new machine.
Doubtful. The problem is that though the main CPU is PowerPC-based like
current Apple chips, it is stripped down, and the Altivec support will be
much lower than in current G5s. Unoptomized, Apple code would run like a G4
on this hardware. They would have to commit to a lot of R&D for their OS to
use the additional 8 processors on the chip, and redesign all their tweaked
Altivec code. It would not be a simple port. A couple of years to complete,
at least.
4.. The parallel nature will make it impossible to program.
This is half-true. While it will be hard, most game logic will be
performed on the traditional PowerPC part of the Cell, and thus normal to
program. The difficult part will be concentrated in specific algorithms,
like a physics engine, or certain AI. The modular nature of this code will
mean that you could buy a physics engine already designed to fit into the
128k limitation of the subprocessor, and add the hooks into your code. Easy
as pie.
5.. The Cell will do the graphics processing, leaving only rasterezation
to the video card. Most likely false. The high-end video cards coming out
now can process the rendering chain as fast as the Cell can, looking at the
raw specs of 256Gflops from the Cell, as opposed to about 200GFlops from
video cards. In two years, video cards will be capable of much more, and
they are already optomized for this, where the Cell is not, so video cards
will perform closer to the theoretical limits.
6.. The OS will handle the 8 additional vector processors so the
programmer doesn't need to.
Bwahahaha! No way. This is a delicate bit of coding that is going to
need to be tweaked by highly-paid coders for every single game. Letting on
OS predictively determine what code needs to get sent to what processor to
run is insane in this case. The cost of switching out instructions is going
to be very high, so any switch will need to be carefully considered by the
designer, or the frame-rate will hit rock-bottom.
7.. The Cell chip is too large to fab efficiently.
This is one myth that could be correct. The Cell is huge (relatively),
and given IBM's problems in the recent past with making large, fast PowerPC
chips, it's a huge gamble on the part of all parties involved that they can
fab enough of these things.
N
NEXT BOX
Tiny new chip packs a lot of power
IBM East Fishkill plant to make microprocessor
By Craig Wolf
Poughkeepsie Journal
What appears to be the hottest microprocessor chip in the world looked even
hotter Monday as IBM Corp., Sony Group and Toshiba Corp. revealed its
performance is 10 times that of current chips.
The tech trio's ''Cell'' chip will be made at IBM's 300-millimeter plant in
East Fishkill this summer to satisfy needs of Sony and Toshiba for a new
generation of broadband, video-hungry home entertainment systems. The plant
already makes a version of the chip being used in computer workstations
suited to game development. The plant is being expanded by IBM and six
partners, including Sony and Toshiba.
New Cell details came out in San Francisco at the International Solid State
Circuits Conference, a major annual technical gathering. Monday's
revelations were whoppers.
8 processors per chip
The chip has eight cores, or separate processors, that operate
synergistically. Industry chatter was predicting four cores. It has run at
speeds of better than 4 gigahertz, or billions of cycles per second,
somewhat ahead of Intel Corp.'s best speeds. It can run several kinds of
software simultaneously, including Linux and proprietary gaming programs.
More details are to come out today, but analysts were impressed already.
''This is still the biggest chip technology advance in probably 20 years,''
said Richard Doherty, research director at Envisioneering Group in Seaford,
Nassau County.
If anything, claims of a 10-fold leap in performance are understated,
Doherty said. ''Our estimate is 10 to 20, so they're being conservative,''
he said.
He added Cell developers said they could have put 16 cores on the same size
chip if they had thought it necessary.
Touted as a ''supercomputer on a chip" by the trio, Cell may well find use
in business environments including supercomputing, but its first and main
function will be to lift the computerized entertainment world to new levels.
Cell is aimed at your house. The chip is expected to be used in Sony's
next-generation Playstation as well as in high-definition television sets.
''It's very flexible,'' said Jim Kahle, an IBM fellow, quoted by the
Associated Press. ''We support many operating systems with our
virtualization technology so we can run multiple operating systems at the
same time, doing different jobs on the system.''
What that could mean, for example, is that gamers in different locations
could play online using Linux, an open-source software widely available
around the world. The chip could handle that work as well as running Sony's
software that controls the game logic and characters.
''Having hierarchical operating systems, if you will, that's a whole big
step in computing,'' Doherty said. ''In entertainment, that's tremendous.''
Cell was developed by the trio at IBM's Austin, Texas, facility beginning in
2001. It contains 234 million transistors in a space of 221 square
millimeters, about the size of a fingernail. It's made with 90-nanometer
process, so called because it creates features that small, a nanometer being
a billionth of a meter.
Executives toasted their teamwork in a statement issued Monday. Masashi
Muromachi, a corporate vice president of Toshiba, said, ''We are proud that
Cell, a revolutionary microprocessor with a brand new architecture that
leapfrogs the performance of existing processors, has been created through a
perfect synergy of IBM, Sony Group and Toshiba's capabilities and talented
resources.''
Whether the team's work eclipses that of leader Intel remains to be seen.
Monday was also the day on which Intel said it was now making a
two-processor chip.
''It's poor timing,'' Doherty said. ''The twin-piston engine comes out the
same day as a V-8.''
IBM East Fishkill plant to make microprocessor
By Craig Wolf
Poughkeepsie Journal
What appears to be the hottest microprocessor chip in the world looked even
hotter Monday as IBM Corp., Sony Group and Toshiba Corp. revealed its
performance is 10 times that of current chips.
The tech trio's ''Cell'' chip will be made at IBM's 300-millimeter plant in
East Fishkill this summer to satisfy needs of Sony and Toshiba for a new
generation of broadband, video-hungry home entertainment systems. The plant
already makes a version of the chip being used in computer workstations
suited to game development. The plant is being expanded by IBM and six
partners, including Sony and Toshiba.
New Cell details came out in San Francisco at the International Solid State
Circuits Conference, a major annual technical gathering. Monday's
revelations were whoppers.
8 processors per chip
The chip has eight cores, or separate processors, that operate
synergistically. Industry chatter was predicting four cores. It has run at
speeds of better than 4 gigahertz, or billions of cycles per second,
somewhat ahead of Intel Corp.'s best speeds. It can run several kinds of
software simultaneously, including Linux and proprietary gaming programs.
More details are to come out today, but analysts were impressed already.
''This is still the biggest chip technology advance in probably 20 years,''
said Richard Doherty, research director at Envisioneering Group in Seaford,
Nassau County.
If anything, claims of a 10-fold leap in performance are understated,
Doherty said. ''Our estimate is 10 to 20, so they're being conservative,''
he said.
He added Cell developers said they could have put 16 cores on the same size
chip if they had thought it necessary.
Touted as a ''supercomputer on a chip" by the trio, Cell may well find use
in business environments including supercomputing, but its first and main
function will be to lift the computerized entertainment world to new levels.
Cell is aimed at your house. The chip is expected to be used in Sony's
next-generation Playstation as well as in high-definition television sets.
''It's very flexible,'' said Jim Kahle, an IBM fellow, quoted by the
Associated Press. ''We support many operating systems with our
virtualization technology so we can run multiple operating systems at the
same time, doing different jobs on the system.''
What that could mean, for example, is that gamers in different locations
could play online using Linux, an open-source software widely available
around the world. The chip could handle that work as well as running Sony's
software that controls the game logic and characters.
''Having hierarchical operating systems, if you will, that's a whole big
step in computing,'' Doherty said. ''In entertainment, that's tremendous.''
Cell was developed by the trio at IBM's Austin, Texas, facility beginning in
2001. It contains 234 million transistors in a space of 221 square
millimeters, about the size of a fingernail. It's made with 90-nanometer
process, so called because it creates features that small, a nanometer being
a billionth of a meter.
Executives toasted their teamwork in a statement issued Monday. Masashi
Muromachi, a corporate vice president of Toshiba, said, ''We are proud that
Cell, a revolutionary microprocessor with a brand new architecture that
leapfrogs the performance of existing processors, has been created through a
perfect synergy of IBM, Sony Group and Toshiba's capabilities and talented
resources.''
Whether the team's work eclipses that of leader Intel remains to be seen.
Monday was also the day on which Intel said it was now making a
two-processor chip.
''It's poor timing,'' Doherty said. ''The twin-piston engine comes out the
same day as a V-8.''
N
Never anonymous Bud
Using a finger dipped in purple ink said:
And cost $500 or more.
Not conducive to mass-marketing of game systems.
R
Rob Stow
NEXT BOX wrote:
[Snip]
Plonk !
[Snip]
Plonk !
D
David Schwartz
Never anonymous Bud said:
It really doesn't matter. Whatever price point you look at ($60, $90,
$200, $400) the rate of performance improvement over time is about the same
(or slightly higher at the low end). Today you can get for $60 what cost
$400 two years ago. You can get for $90 what cost $300 last year.
A dedicated graphics chipset that is designed as part of an integrated
system that will be build as a large quantity of identical units changes the
economics significantly. A large part of the cost of selling a graphics card
is the physical interface, packaging, testing, shipping, advertising,
stocking, tooling runs, and customer support. When the graphics chipset is
part of a larger unit, all of these costs are dramatically lower. So an
integrated game system can contain the equivalent of a $200 graphics card
for an added cost of only about $50.
Due to economics of scale and buying in bulk, the price different
between the equivalent of a $200 graphics card and the equivalent of a $300
graphics card is probably negligible. Remember, the graphics chip vendors
want to push up their ability to produce high-end chips in quantity anyway.
This gives them a competitive edge in the PC graphics market.
DS