XP 3500 socket 939 high cpu temps?

  • Thread starter Thread starter Don Burnette
  • Start date Start date
Wes Newell wrote:
[...]

I had a point-by-point reply, but I decided against posting it since I can
see this turning into a bit of a flamewar.

In any case, I recommend you read the AMD tech docs, as opposed to marketing
material by chipset manufacturers. If you look at AMD tech docs, you'll see
that the northbridge consists of the system request queue (SRQ) which sits
between the two dies (one left unconnected :) ), the APIC, and the crossbar.
The crossbar sits between the memory controller, the 3 HT links, and the
SRQ.

In a traditional (dual-CPU capable, PTP busses) system, this is more or less
a standard northbridge that you would have seen if the chipset ran the AGP
bus off the southbridge (can't remember the ones that did, but I remember
that performance wasn't too hot), or didn't support AGP at all.

Calling a piece of glue logic that essentially just converts between HT and
VLink a northbridge, when there's a much more northbridge-like construct
inside the CPU, isn't the most obvious decision IMO. Sorta similar to if a
K7 Via chipset was made up of three chips: one that converted between EV6
and VLink, one that did the normal northbridge duties (AGP/DRAM/PTP links if
SMP), and one that did the normal southbridge duties (PCI, integrated
bits'n'bobs, etc). Would the interconnect glue be the northbridge?

I think with the K8, or any HT-based system, the terms northbridge and (and
possibly southbridge as well) can't really be used. You just have a
daisy-chained series of devices. For example, the ALi "northbridge" is
nothing more than an hypertransport tunnel with an AGP interface (in fact
it's just a rebadged AMD 8151, which is called a "Hypertransport AGP tunnel"
by AMD). The SiS and Via "nortbridges" are pretty much the same thing
feature-wise, though also feature a interconnect translater (to VLink to
Mutiol).

Northbridge, IMO, should be reserved for systems that have a definate
northbridge-like chip. If northbridge functionality is split up over
multiplie bits of the system, then either don't talk about northbridges at
all (preferable), or call the most northbridge-like bit the northbridge.
 
I think with the K8, or any HT-based system, the terms northbridge and
(and possibly southbridge as well) can't really be used. You just have a
daisy-chained series of devices. For example, the ALi "northbridge" is
nothing more than an hypertransport tunnel with an AGP interface (in fact
it's just a rebadged AMD 8151, which is called a "Hypertransport AGP
tunnel" by AMD). The SiS and Via "nortbridges" are pretty much the same
thing feature-wise, though also feature a interconnect translater (to
VLink to Mutiol).
Click to expand...
There's only one difference between the K8 and previous x86 cpu's
conserning the northbridge, and that's that the memory controller has been
moved off the northbridge and onto the cpu. This along with the cpu's
extra HT links is what enhances performance in both single and multicore
systems. All other functions of the standard north/south bridge system are
still there. They still use the same achitecture, etc. It's just they have
a faster system bus because the system bus is now an HT link bus. So what
is the system bus? It's just another name for FSB and it does the same
thing as the FSB in previous K6, K7, etc cpu's except for the memory
controllers. It controls IO to all other external devices through the
north/south bridge, with the exception of memory. This includes AGP, PCI,
PCI-E, mouse/keyboard, and whatever else the chipset manufacturer wants to
pack into it, generally called the feature set. The chipset manufactures
have not changed the name of these devices to confuse people. And that
keeps it simple, and I agree. OTOH, many people now think the K8 doesn't
have a FSB when in fact the name FSB name has just been dropped in favor
of calling it just the system bus, which is fine with me as it was also
called this in the K7 series if you get right down to it. So in the K7 the
cpu, connected to all other devices through the FSB to the northbridge and
then the southbridge (including system ram). The K8 does the exact same
thing with these exceptions. The memory and only the memory connects
direct to the cpu instead of the northbridge. That they now call the FSB
only the system bus is fine. Even calling it the HT bus/link is fine with
me too as long as everyone realizes that there can be more than one HT
link in a system, serving totally different functions. System bus is much
more specific. And since the chipset manufacturers decided not to change
what they call the chipset (northbridge/southbridge) who am I to argue
with them. It only makes sense to me. The fact that the system bus is now
serial instead of parelell really has doesn't matter to me. It's still the
system bus only much faster using a different architechture.

While we may never agree on this terminology it's what it is, and I hope
others lurking will learn something from this thread.
 
SiS755
( North Bridge Chipset )
SiS Chipset Supports AGP8X for AMD Athlon 64 Platform

http://www.sis.com/products/chipsets/oa/athlon64/755.htm

SIS calls their link between the north adn south Multitol. VIA, something
else and others yet something else. It's still a seperate bus in any case.
Click to expand...


Interesting. Wes, has your computer been complaining to you lately?
According to SIS, they have Hypertransport *complaint* bus driver
technology. lol

DougH
 
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