Gaming AMD vs Intel

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You're just a little more than confused. The CPU doesn't support AGP, PCI,
PCI-E or much of anything else except the ram directly. The rest still are
still functions of the chipset. The only thing that the CPU now supports
directly is the memory. All other system devices/buses are handled the
same way as the K7 was, over the FSB, or if you prefer, the HT Link
between the cpu and chipset.
Click to expand...

You have just proved your complete misunderstanding of what is on the K8
die and what the HT I/O-link is used for. All CPU memory accesses mapped
to I/O devices, such as AGP/PCI-e, or any PCI device must be trapped in the
CPU's "north bridge" sub-set and diverted to the HT I/O link; obviously the
corresponding MTRRs and associated logic *must* be on the CPU die. Same
for CPU cache snooping - previously a north bridge/FSB function and now
incorporated into the CPU.

Apart from CPU I/O reads/writes and interrupts, a minor part of FSB traffic
"volume", the HT I/O link has nothing in common with a FSB. The major
volume of traffic on the K8 HT I/O-link, viz. DMA transfers, is handled and
routed internally in the north bridge (MC Hub) of a FSB type system.
 
You have just proved your complete misunderstanding of what is on the K8
die and what the HT I/O-link is used for. All CPU memory accesses mapped
to I/O devices, such as AGP/PCI-e, or any PCI device must be trapped in the
CPU's "north bridge" sub-set and diverted to the HT I/O link; obviously the
corresponding MTRRs and associated logic *must* be on the CPU die. Same
for CPU cache snooping - previously a north bridge/FSB function and now
incorporated into the CPU.
Click to expand...
No, I understand that since the memory bus is now split out of the chipset
northbridge, that there has to be some control in the cpu to split address
the proper bus. And once sent to the each of the other devices (Chipset or
memory controller) it has to be routed accordingly by that device. What
this internal logic (called a northbridge by AMD) doesn't do is actual
route the data to the proper destination of the final device. This is
still done in the chipset just as it was done in the K7. In simpler terms,
the internal cpu logic just strips out reads/ writes to memory addresses
and sends them to internal memory controller instead of out the FSB (HT
Link) as the K7 did. I did similar things when designing the products I
used to manufacture and sell. it's just logic.
Apart from CPU I/O reads/writes and interrupts, a minor part of FSB
traffic "volume", the HT I/O link has nothing in common with a FSB. The
major volume of traffic on the K8 HT I/O-link, viz. DMA transfers, is
handled and routed internally in the north bridge (MC Hub) of a FSB type
system.
Click to expand...

I don't consider the part you consider to be minor, minor. I consider it
the major part. And I assume AND does to, otherwise why replace the the
EV6 bus with HT. It's a fact that with the memory bus now split out of the
FSB, that the required bandwidth of the FSB (HT Link) dropped
dramatically, since most of the bandwidth in previous FSB applications was
taken up by memory read/writes. Maybe I should be blaming the Mb
manufactures for using FSB for a term for setting the cpu clkin to begin
with. CPU Host Clock would have been more specific anyway. That would have
also done away with the real speed of the FSB fiasco. All in all, I'm
getting to the point where I don't much care anymore.
 
No, I understand that since the memory bus is now split out of the chipset
northbridge, that there has to be some control in the cpu to split address
the proper bus. And once sent to the each of the other devices (Chipset or
memory controller) it has to be routed accordingly by that device. What
this internal logic (called a northbridge by AMD) doesn't do is actual
route the data to the proper destination of the final device. This is
still done in the chipset just as it was done in the K7.
Click to expand...

The K8 does things differently from the K7 - it's obvious but see below.
In simpler terms,
the internal cpu logic just strips out reads/ writes to memory addresses
and sends them to internal memory controller instead of out the FSB (HT
Link) as the K7 did. I did similar things when designing the products I
used to manufacture and sell. it's just logic.
Click to expand...

There have been MTRRs in the CPU for a while now but more to do with
cachability and write combining - there are *additional* structures & logic
elements in the K8 core which used to be part of north bridge action...
because of the need to arbitrate to main memory or I/O device mapped
memory... and of course the legacy "reserved memory" space.
I don't consider the part you consider to be minor, minor. I consider it
the major part. And I assume AND does to, otherwise why replace the the
EV6 bus with HT. It's a fact that with the memory bus now split out of the
FSB, that the required bandwidth of the FSB (HT Link) dropped
dramatically, since most of the bandwidth in previous FSB applications was
taken up by memory read/writes.
Click to expand...

The HT I/O-link can also be required to carry high bandwidth data... as
already stated, all the DMA which used to be internal to the NB.
Maybe I should be blaming the Mb
manufactures for using FSB for a term for setting the cpu clkin to begin
with. CPU Host Clock would have been more specific anyway. That would have
also done away with the real speed of the FSB fiasco. All in all, I'm
getting to the point where I don't much care anymore.
Click to expand...

The mbrd mfrs have not helped here.
 
Wes Newell said:
I don't consider the part you consider to be minor, minor. I consider it
the major part. And I assume AND does to, otherwise why replace the the
EV6 bus with HT. It's a fact that with the memory bus now split out of the
FSB, that the required bandwidth of the FSB (HT Link) dropped
dramatically, since most of the bandwidth in previous FSB applications was
taken up by memory read/writes. Maybe I should be blaming the Mb
manufactures for using FSB for a term for setting the cpu clkin to begin
with. CPU Host Clock would have been more specific anyway. That would have
also done away with the real speed of the FSB fiasco. All in all, I'm
getting to the point where I don't much care anymore.
Click to expand...


You still haven't grasped the fundamental difference between a point-to-point
serial link and a shared bus. HT is a point-to-point serial link. It provides
full bandwidth between a processor socket and either another socket (in coherent mode) or a
southbridge (e.g. Serverworks HT2000) in non-coherent mode. Since an Opteron
has 3 HT links, the inter-socket communications are at full HT bandwidth and
are not perturbed in any way by IO traffic over a non-coherent link.

The inter-socket communications consist primarily of coherency traffic
(probes, (snoops on a FSB)) and memory transfers when one socket requires
data from DRAM controlled by another socket.

Because the links are point to point, the non-coherent HT link between
the processor socket and southbridge gets full bandwidth while the coherent link(s)
between processor sockets also get full bandwidth.

Contrast this with the shared bandwidth on a FSB and you'll easily see
the performance advantages of a point-to-point link like the HT.

The advantages hold true for sempron64 and athlon64 as well, even with
one HT link, because the HT is never used for memory traffic, unlike a
traditional FSB which carries memory and I/O traffic.

scott
 
Scott Lurndal said:
You still haven't grasped the fundamental difference between a
point-to-point
serial link and a shared bus. HT is a point-to-point serial link. It
provides
full bandwidth between a processor socket and either another socket (in
coherent mode) or a
southbridge (e.g. Serverworks HT2000) in non-coherent mode. Since an
Opteron
has 3 HT links, the inter-socket communications are at full HT
bandwidth and
are not perturbed in any way by IO traffic over a non-coherent link.

The inter-socket communications consist primarily of coherency traffic
(probes, (snoops on a FSB)) and memory transfers when one socket
requires
data from DRAM controlled by another socket.

Because the links are point to point, the non-coherent HT link between
the processor socket and southbridge gets full bandwidth while the
coherent link(s)
between processor sockets also get full bandwidth.

Contrast this with the shared bandwidth on a FSB and you'll easily see
the performance advantages of a point-to-point link like the HT.

The advantages hold true for sempron64 and athlon64 as well, even with
one HT link, because the HT is never used for memory traffic, unlike a
traditional FSB which carries memory and I/O traffic.

scott
Click to expand...

Scott, you don't seem to have absorbed the essense of this thread which
seems to be not a discussion of the merits of HT but some sort of
argument about whether it is acceptable to refer to a HT link as a bus,
and whether the chip connected to by said link from an amd processor is a
"north bridge" or something else unnamed, and whether the HT link in
question connecting the cpu to said chip is a "front side bus".

I hope this clears up things for you.

del
 
Del Cecchi said:
Scott, you don't seem to have absorbed the essense of this thread which
seems to be not a discussion of the merits of HT but some sort of argument
about whether it is acceptable to refer to a HT link as a bus, and whether
the chip connected to by said link from an amd processor is a "north
bridge" or something else unnamed, and whether the HT link in question
connecting the cpu to said chip is a "front side bus".

I hope this clears up things for you.

del
Click to expand...

Actually once upon a time this thread was about AMD or Intel for gaming :)
 
Scott said:
Del,

It is clearly not a bus. The northbridge is integrated into the
processor die. The other end of an HT link is either another
processor socket or a southbridge.

Hope that answers your query.

scott
Click to expand...

North bridge, Southbridge, whatever.

Link, buss, likewise. The HT Link is a bus. A bus is not always a
link. At least among the folks I talk to. Hard to get too excited
about the terminology.

del (followups trimmed)
 
Del Cecchi said:
Scott, you don't seem to have absorbed the essense of this thread which
seems to be not a discussion of the merits of HT but some sort of
argument about whether it is acceptable to refer to a HT link as a bus,
and whether the chip connected to by said link from an amd processor is a
"north bridge" or something else unnamed, and whether the HT link in
question connecting the cpu to said chip is a "front side bus".

I hope this clears up things for you.

del
Click to expand...

Del,

It is clearly not a bus. The northbridge is integrated into the
processor die. The other end of an HT link is either another
processor socket or a southbridge.

Hope that answers your query.

scott
 
It is clearly not a bus. The northbridge is integrated into the
processor die. The other end of an HT link is either another
processor socket or a southbridge.

Hope that answers your query.
Click to expand...
It's an answer, just wrong. First, it is a bus, and second, it doesn't
connect to the chipset southbridge, it connects to the chipset
northbridge. Although AMD refers to the logic that splits the memory data
to the internal memory controller a northbridge, well I guess they can
call it whatever they like. The HT link (FSB, CPU bus or whatever you
want to call it) that connects to the chipset connects to the chipset
northbridge (the SIS755 In my case). The SIS755 connects to the
southbridge over a preprietary MUtiol bus. I guess at this point we have
to except that there's 2 northbridges. One in the CPU, and one in the
chipset. Either that or call either AMD or ALL the chipset manufactures
liars for calling there chip a northbridge too. Clearly, what used to be
all done in the chipset northbridge is now partly done in both the cpu and
chipset.
 
Actually once upon a time this thread was about AMD or Intel for gaming :)

Hmmm...


Was that my origonal question

Well I'll be damned...
 
It's an answer, just wrong. First, it is a bus, and second, it doesn't
connect to the chipset southbridge, it connects to the chipset
northbridge. Although AMD refers to the logic that splits the memory data
to the internal memory controller a northbridge, well I guess they can
call it whatever they like. The HT link (FSB, CPU bus or whatever you
want to call it) that connects to the chipset connects to the chipset
northbridge (the SIS755 In my case). The SIS755 connects to the
southbridge over a preprietary MUtiol bus. I guess at this point we have
to except that there's 2 northbridges. One in the CPU, and one in the
chipset. Either that or call either AMD or ALL the chipset manufactures
liars for calling there chip a northbridge too. Clearly, what used to be
all done in the chipset northbridge is now partly done in both the cpu and
chipset.
Click to expand...

Well, where there are still two chips for the "chipset" -- not the case for
nForce3/4 -- there is a *small* amount of north bridge functionality in the
chip at the other end of the CPU<->HT I/O-link: a mezzanine bus to AGP &
PCI-X or the PCI-e x16 graphics link... and maybe some other high
priority/speed link like multi-Gig network but that's piddly compared with
a memory controller and all the arbitration logic plus snooping to the FSB
in a real north bridge. In fact Intel dropped the term North Bridge years
ago and uses MCH for umm, Memory Controller Hub... and AMD would call your
"SIS755 north bridge" a HyperTransport Tunnel. Says it all from my POV -
it doesn't even talk like a duck.:-)
 
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