Gaming AMD vs Intel

[Del Cecchi]

I suggest you understand what a bus is, and forget what the popular
press
says.


There is no such "proof". The definition of a "bus" is much older than
even you. A buss is a multi-drop utility. ...kinda like what you take
to
work. A point-to-point facility is never referred to as a "bus".

Around where I work that isn't true. Bus is used as a generic term for a
collection of wires making up a single construct. But maybe your custom
is different.
snip

Oh, and what would your credentials be to call yourself a system
"expert"
or *architect*? You've certainly shown no such expertice here! The HT
architects certainly do *not* call the HT a bus, nor a front-side
*anything*.

<snip - bedtime; zzzzzzz>

Don't know frontside from my backside. That seems to be a PC thing which
isn't really my background. But I have hung around some experts and they
are not so dogmatic about what a bus is and what a link is. The number
of drops really has little bearing on it.

And most of the experts I know don't call themselves experts....

del

 

[George Macdonald]

Suggest you read this. One of thousands that claim it's a bus.

http://www.free-definition.com/Front-side-bus.html

But you forgot to read it: under HyperTransport: "Not technically a front

I'm not wasting any more time citing crap for you. The proof is down
below, which you tend to ignore.

A FAQ is *not* a tech reference.

The cpu to system memory function was just one of many functions the FSB
does. it still has cpu to memory functions and feeds data to/from the
memory on the video card, the cache memory on each hard drive, memory on
other cards, etc, etc, etc.

The CPU<->main-memory traffic is by far the principle function of FSB...
and *is* what the name FSB is derived from. Those others are all I/O and
even where memory mapped, as for video, further illustrate the fact that
north bridge functionality has been implemented in the CPU die.

I meant the chipset northbridge.

See below - no such animal!

So, I'm supposed to tell someone that the CPU clockspeed is determined by
the multiplier times the I/O connection speed. Right. Would you care to
guess how many I/O connections there are in a basic PC system, 100,
1000, more than that?

You can call it the "(system) base clock", which is what it is.

Actually you can get a functioning system without external ssytem memory.
I'd sure like to see you use a system without a video output, or a storage
device, or any of the other functions that go over the FSB. They have
them, but they're usually used in standalone places as embedded. So, to
me, the memory is not the most important function, but even if it was,
it's still just ONE of many.

We're talking about (AMD) PC architecture here.

So, if it's not a FSB because the memory bus is now seperate, then the
memory bus is the FSB. Now I'm wondering what I'm going to call my car
when I take the removable dvd player out of it. Can't call it a car
anymore can I. Lost the cigar lighter, no more car.

You must be Irish...?... or drunk?

Sorry, my K8 system isn't designed the same way as it is in the diagram
you reference, and I doubt yours is either. Look at it closely. look at
the northbridge, and then look at the other side. What's changed other
than the name? One thing, the memory bus moved to the cpu.

And that is a *BIG* change - think about it: the principle function of the
CPU<->HT-link is now to carry all DMA traffic between I/O devices and
main-memory, in both directions... not a FSB function at all... bears no
resemblance.

Let's see. I've proven the HT link can be a bus. I've proven the HT link
is a FSB when connected betwen the cpu and chipset. That's it for me. if
you need proof from someone other than the people that develope HT
technology you'll have to get it elsewhere.

All you've proven is that you don't know what an FSB is nor what part it
plays in a PC system.

 

[Tony Hill]

It calls it a bus (a Front Side bus at that) in the portion you snipped
out and you know it. I don't know why you cut it out. it only makes you
look trollish. Here's some more info for you.

http://www.free-definition.com/Front-side-bus.html

Hmm, from this link, at the bottom of the chart:

"*** - Athlon 64, FX, and Opteron processors have a memory controller
on the CPU die, which replaces the traditional FSB"

http://www.free-definition.com/category/Computer_bus

Try this one:

http://www.free-definition.com/Computer-bus.html

"In computer architecture, a bus is a subsystem that transfers data or
power between computer components inside a computer or between
computers. Unlike a point-to-point connection, a bus can logically
connect several peripherals over the same set of wires."

Hypertransport is a point-to-point connection, as is PCI-Express.
GTL+ and PCI are buses.

 

[Tony Hill]

You wouldn't know the definition if it bit you on the ass. But, just to
show how stupid this response is, the frontside bus was point to point, as
was the back side bus. The same could be said for the memory bus. IOW's
you don't know wtf you are talking about.

Uhh ?!?! The GTL bus used in the PPro was DEFINTIELY a multi-point
bus. You can hang up to 4 CPUs off of that bus. This is still true
(at least in some situations) for the AGTL+ bus that Intel still uses
for their P4 and Xeon CPUs.

Similarly the backside bus in the PPro, PII and early PIII chips could
definitely have more than one memory device hung off the back of it.
If my memory is serving me, some Xeon CPUs had up to 4 cache chips on
a single bus. You can't do that with a point-to-point link!

Keeping up with the memory bus it DEFINITELY is a multidrop bus with
only one popular exception that I'm aware of (RDRAM). How else do you
think you can hang more than one DIMM off a single memory bus?

EV6, on the other hand, was not a bus by the strict multidrop
definition of things in that you could NOT hang more than one
processor off the bus. That's why AthlonMP systems (and DEC/Compaq/HP
Alpha systems before it) had one bus per processor. This is a large
part of the reason why you never saw quad AthlonMP systems, only dual
processor ones. Now, that being said, EV6 resembled a bus in most
other respects, which is why I said that it kind of blurred the lines
between a traditional bus and a strictly point-to-point connection.


Now, just how strictly one follows some of these definitions of what a
"bus" is depends on the reader. I know many people (myself included)
would tend to take shortcuts most of the time. Generally speaking I
would quite freely refer to EV6 as a "bus" rather than going through
the above explanation. I'm sure I've even been known to call
PCI-Express or Hypertransport a "bus" from time to time, though I
still recognize that it's not correct.

9. How does HyperTransport technology compare to other bus technologies?

*this is the relevent part*
HyperTransport was designed to support both CPU-to-CPU communications as
well as CPU-to-I/O transfers, thus, it features very low latency.
Consequently, it has been incorporated into multiple x86 and MIPS
architecture processors as an integrated front-side bus.

That's rather poorly worded on their part and actually contradicts
other parts of the same article where they (correctly) state that
Hypertransport is not a bus at all. As mentioned above though, people
take shortcuts, sometimes even when they know it's not really correct.

 

[keith]

: On Fri, 09 Sep 2005 10:01:26 -0500, Del Cecchi wrote:
:
<snip>

::
:: The last paragraph you quote, shown above, is Clintonian at best,
:: with respect to comparing the physical aspects of HT and PCI-E.
:
: You snipped the portion I had highlighted. I didn't even read this
: part. Nor do I have any comments on it. If you have a problem with
: it. i suggest you contact the people that wrote it. If Clintonian
: refers to refers to our lying crooked x pres, those are are
: fighting words. I never voted for the lowlife.

Oh how interesting. So you voted for the current crooked, lying
president? Oops, forgot to throw in "incompetent" as he gives a whole new
meaning to the word. LOL!

....and your contribution here is??? Yutz! LOL!

 

[keith]

Around where I work that isn't true. Bus is used as a generic term for a
collection of wires making up a single construct. But maybe your custom
is different.

Evidently. A "bus" is something that anyone can hook to (limitations, of
course). Sometimes people get sloppy with terminology though.

snip

Don't know frontside from my backside.

Gee, Del! Maybe you should ask your wife? ;-)

That seems to be a PC thing which isn't really my background.

It is, starting with the P6. Actually back-side caches were known before.
....as opposed to look-aside, look-through, etc.

But I have hung around some experts
and they are not so dogmatic about what a bus is and what a link is. The
number of drops really has little bearing on it.

It makes a big difference.

And most of the experts I know don't call themselves experts....

I asked *hoim* what his expertice was. He didn't answer.

 

[keith]

And people talk about the power bus even when it is a grid. Just like
they talk about the clock tree when it is a grid. And real designers
sometimes talk about the HT bus or the RIO bus, or the GX bus even when
it is a link more than a bus.

People call cyan, blue too. Because people get sloppy, doesn't change the
meaning of words. In technical writing, words do have meanings.

 

[Del Cecchi]

People call cyan, blue too. Because people get sloppy, doesn't change
the
meaning of words. In technical writing, words do have meanings.

Well, you wanna be picky, cyan is blue. And taupe is tan. And a link is
a bus. Just a special case is all. Just what is the difference? If I
only have two pins on a bus connection, like many PCI-X implementations,
does that make it not a bus?

I was just reporting what folks I hang around with during the week say.
What's the big deal? Saying HT is a link is more specific than saying it
is a bus, but I consider it to also be a bus. It's a floor wax and a
dessert topping.

del

 

[Wes Newell]

: On Fri, 09 Sep 2005 10:01:26 -0500, Del Cecchi wrote:
:
<snip>

::
:: The last paragraph you quote, shown above, is Clintonian at best,
:: with respect to comparing the physical aspects of HT and PCI-E.
:
: You snipped the portion I had highlighted. I didn't even read this
: part. Nor do I have any comments on it. If you have a problem with
: it. i suggest you contact the people that wrote it. If Clintonian
: refers to refers to our lying crooked x pres, those are are
: fighting words. I never voted for the lowlife.

Oh how interesting. So you voted for the current crooked, lying
president? Oops, forgot to throw in "incompetent" as he gives a whole new
meaning to the word. LOL!

I hate to tell you this, but the current president, G. Bush never ran
against Clinton. If you want to comment on something or throw a dig at
someone, it helps if you know wtf you are talking about. That said, I sure
as hell didn't vote for Gore.

 

[Wes Newell]

Hmm, from this link, at the bottom of the chart:

"*** - Athlon 64, FX, and Opteron processors have a memory controller
on the CPU die, which replaces the traditional FSB"

Note the wording. It doesn't say it replaces the FSB. It says it replaces
the traditional FSB. The FSB is still there, jst not in a tradidtional
sense, since the memory has it's own path now. I'll tell you what. You can
call it whatever you like, and I'll do the same.

Try this one:

http://www.free-definition.com/Computer-bus.html

"In computer architecture, a bus is a subsystem that transfers data or
power between computer components inside a computer or between
computers. Unlike a point-to-point connection, a bus can logically
connect several peripherals over the same set of wires."

But if you use this definition, there was never a FSB, or BSB bus
as these were both point to point connections. Was not the FSB of the
original Pentium Pro point to point (cpu to chipset)? And this defintition
also disagrees with lots of other definitions of bus, and lastly, if my
system has only one memory slot, does that mean my system doesn't have a
memory bus? One sometimes one has to think logical rather than just take
something at face value.

Hypertransport is a point-to-point connection, as is PCI-Express. GTL+
and PCI are buses.

Along with HyperTransport, PCI-Express is also defined as a Computer bus.

 

[nobody]

On Fri, 09 Sep 2005 18:23:25 -0400, George Macdonald

....snip...

If we allow a bit of slack and call the on-die L2 cache connection a BSB,
we can call the K7s', P4s', P-Ms' connection to the chipset a FSB - after
all it carries the same traffic as a FSB. AMD has used this terminology
for its K7 architecture though some have argued with that. With the K8 the
HT link to to the I/O sub-system, however, there is no CPU<-> memory
traffic, which is the principal function of a FSB and is the derivation of
the name; the up/down HT link doesn't even serve the same functions as a
FSB.

....snip...

"no CPU<-> memory traffic"
Correct for uniprocessor system. As soon as we get to dual (trust me
on this - I'm typing this on 2x Opteron 242 on MSI master2-far board)
HT starts carrying CPU<-> memory traffic. It is especially true in
case of more than half dual Opty board out there (including mine)
where all RAM is hanging off one CPU, and the other accesses it
through HT.

NNN

 

[Big_Pig]

Since there is no FSB to use as a reference for the CPU-core's
clockspeed (as well as some of the other clocks), we need something else
to provide the required reference clock signal.

The solution to this problem is a 200MHz base-clock provided to the
processor by the on-board clock-generator on all 8th-Generation
platforms.

This Article will explain how clocks are generated on an AMD
8th-Generation platform.
http://forums.amd.com/index.php?showtopic=55881

 

[Tony Hill]

But if you use this definition, there was never a FSB, or BSB bus
as these were both point to point connections. Was not the FSB of the
original Pentium Pro point to point (cpu to chipset)?

No it most definitely was not. You could hang up to 4 PPro processors
off the same bus.

And this defintition
also disagrees with lots of other definitions of bus, and lastly, if my
system has only one memory slot, does that mean my system doesn't have a
memory bus?

If you're using SDRAM or DDR SDRAM then the bus connects to each
individual chip on the module. Unless you've only got a single memory
chip on your single DIMM then this is definitely not a direct
point-to-point connection.

Besides, it's more a question of what the bus is capable of, not so
much what it is actually being used for. Just because the P4
processor itself is only capable of working in a single-processor
setup doesn't change the fact that the AGTL+ bus that it uses can be
used for up to 4 processors on the same bus (as seen in some Xeon
systems).

 

[Shawk]

No it most definitely was not. You could hang up to 4 PPro processors
off the same bus.


If you're using SDRAM or DDR SDRAM then the bus connects to each
individual chip on the module. Unless you've only got a single memory
chip on your single DIMM then this is definitely not a direct
point-to-point connection.

Besides, it's more a question of what the bus is capable of, not so
much what it is actually being used for. Just because the P4
processor itself is only capable of working in a single-processor
setup doesn't change the fact that the AGTL+ bus that it uses can be
used for up to 4 processors on the same bus (as seen in some Xeon
systems).

You guys must be a barrel of laughs down the pub.... ;-)

Could ya knock of the non-technical game group from future posts pls?

 

[Wes Newell]

Since there is no FSB to use as a reference for the CPU-core's
clockspeed (as well as some of the other clocks), we need something else
to provide the required reference clock signal.

The solution to this problem is a 200MHz base-clock provided to the
processor by the on-board clock-generator on all 8th-Generation
platforms.

And that's exactly how previous generations platforms did it too.

This Article will explain how clocks are generated on an AMD
8th-Generation platform.
http://forums.amd.com/index.php?showtopic=55881

This is a great article, but there's really no difference in the system
clock source of the K7 and K8. They both use the clkin signals. Previously
this clock was called FSB frequency or FSB clock or whatever a board
manufacurer wanted to use to set the clock generator. I think most used
FSB Frequency, but I haven't looked at all the boards bioses. So now comes
the K8 and in their wisdom (or lack of it IMO), thee decide the new bus
type of HT link shouldn't use FSB as the name like the previous K7 EV6
type bus. And that would have been fine if they would come up with another
name to set this clock. I haven't looked at many K8 boards, but it's
designated as System Bus in my bios. The big problem with that name is
that a system bus can any in the system, and isn't specific enough. Same
goes for HT link, which is really a name for a technology like EV6 is, and
is used in many applications than just the K8 CPU's. Not to mention there
can be multiple HT links in a system, so how do you know which one they're
talking about unless it spelled out. Looking back, it would have been
much better to use something like System Clock Gen or CPU Clock Gen for
this setting rather than FSB, but since we were shouldered with FSB, it
finally became known as the connection between the CPU and chipset, which
in fact it is, and that this was the setting to chnage to set the internal
cpu clock... Now that there's no FSB designated for the K8, there's also
no desgination one would easily recognize. So did AMD do away with the
FSB, or just the name because they wanted more exposure for HT or some
other reason. I contend, it was just the name they wanted to change since
the actual traces on the MB still go from the CPU to the chipset just like
previous FSB's with the exception of the memory bus. Had they keep the FSB
name, or even called it the HT FSB, there wouldn't have been the confusion
there is now. Fankly I don't care much. But since many peole don't like
the term FSB used with the K8, I'm going to start telling people to raise
the clkin frequency to the cpu to set the cpu speed and let them worry
about what there board maker called it in the bios. Now since the FSB
term was used to set clkin on previous cpu's, why is it now all of a
sudden taboo?

 

[NoNoBadDog!]

Your entire premise is wrong.

Hypertransport is a High speed, packet based control and communication
protocol. It supports the Direct Connect Architecture of the AMD Athlon64
and Turion64 processors. The processor does not use the Northbridge to
communicate to Memory/AGP/PCI/PCI-E, so there is *no* FSB speed there. The
traditional Northbridge legacy set is handled by the chip, as is the
Southbridge, but for the Proc, RAM and video there is no FSB, just the
speed/bandwidth of the H/T bus (800, 1000, 1600 or 2000). In addition, the
communication is duplex under Hypertransport, versus simplex under NB-FSB.

Bobby

 

[Wes Newell]

Your entire premise is wrong.

Hypertransport is a High speed, packet based control and communication
protocol. It supports the Direct Connect Architecture of the AMD Athlon64
and Turion64 processors. The processor does not use the Northbridge to
communicate to Memory/AGP/PCI/PCI-E, so there is *no* FSB speed there. The
traditional Northbridge legacy set is handled by the chip, as is the
Southbridge, but for the Proc, RAM and video there is no FSB, just the
speed/bandwidth of the H/T bus (800, 1000, 1600 or 2000). In addition, the
communication is duplex under Hypertransport, versus simplex under NB-FSB.

You're just a little more than confused. The CPU doesn't support AGP, PCI,
PCI-E or much of anything else except the ram directly. The rest still are
still functions of the chipset. The only thing that the CPU now supports
directly is the memory. All other system devices/buses are handled the
same way as the K7 was, over the FSB, or if you prefer, the HT Link
between the cpu and chipset.

 

[George Macdonald]

On Fri, 09 Sep 2005 18:23:25 -0400, George Macdonald

...snip...
...snip...

"no CPU<-> memory traffic"
Correct for uniprocessor system. As soon as we get to dual (trust me
on this - I'm typing this on 2x Opteron 242 on MSI master2-far board)
HT starts carrying CPU<-> memory traffic. It is especially true in
case of more than half dual Opty board out there (including mine)
where all RAM is hanging off one CPU, and the other accesses it
through HT.

Of course but that's really CPU<->CPU traffic... which is why I made a
point of clearly specifying the "HT link to the I/O sub-system". Lifting
quoted text out of context only confuses the issue.

 

[George Macdonald]

Since there is no FSB to use as a reference for the CPU-core's
clockspeed (as well as some of the other clocks), we need something else
to provide the required reference clock signal.

The solution to this problem is a 200MHz base-clock provided to the
processor by the on-board clock-generator on all 8th-Generation
platforms.

This Article will explain how clocks are generated on an AMD
8th-Generation platform.
http://forums.amd.com/index.php?showtopic=55881

This one doesn't have any mistakes -
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24707_PUB.PDF

 

[NoNoBadDog!]

You're just a little more than confused. The CPU doesn't support AGP, PCI,
PCI-E or much of anything else except the ram directly. The rest still are
still functions of the chipset. The only thing that the CPU now supports
directly is the memory. All other system devices/buses are handled the
same way as the K7 was, over the FSB, or if you prefer, the HT Link
between the cpu and chipset.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm

Re-read what I wrote...I did not say that it did, but that the
hypertransport bus allows greater bandwidth and duplex operations. The
memory controller accesses the cache and RAM data.
The NB is legacy, while the SB still functions in a traditional manner.

Bobby