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David Kanter
The L2 is, but not the L3. The L3 clearly can't be mutually exclusive
since it is a shared cache, and there can stuff in each core's private
caches that can also be in the shared cache.
The L3 could be exclusive, but it looks like it isn't. Data in the L3
can (but will not always) remain there, once it is pulled to the L1.
It's an interesting idea, you can possibly outfit a processor's entire
system RAM in ZRAM if you put these things off-die.
Not really. ZRAM probably uses a lot more power than DRAM.
Yes, that too.
Still clearly not as much of an increase as if you had to do 16MB of
cache in SRAM rather than ZRAM.
My point is that you claimed 16MB of ZRAM was not a very large
increase from 2MB of SRAM. It is.
For ZRAM1, they actually required comparator cells to distinguish
between a logical 0 and 1, since the voltage differentials were so
miniscule.
Again, doesn't sound that hot. the second version is more
interesting.
DK