Yousuf Khan said:
Not offering any opinions myself, just relaying an article:
http://www.osnews.com/story.php?news_id=6757
Yousuf Khan
Itanium is a ugly architecture,
While I like the predication because you can describe
both paths of the branches and not take a
branch mis-prediction hit, but....
First, The software-pipelining feature is extremely
convoluted piece to understand. It uses the
predication registers and the stack engine
together to work, but what happens when you are
already using the predication registers??
Plus this makes the RSE engine more complicated.
Alot of the stuff is done behind some scene.
Or with alot of hand waving. Which is bad
when you are programming in Assembly language.
Believe me, I've done programming in IA64 Assembly
language for work and alot of the examples
given by Intel I could not make heads or tails.
Second, because of the instructions bundles/groups
design, you have to pad the instruction slots
with NOOPs if you can't find exactly three instructions
per group. Hence, the instruction cache is effectively very small.
Third, There is NO integer multiple nor integer divide!!!
So you have to move the values over to the
Floating point unit. Well, what happens if the
FPU is busy doing loops?? Do you want to
interrupt whatever the FPU is doing just for
your integer multiplication that integer ALUs can't do??
If you look carefully at the IA64, It's really a
descendant of HP's PA RISC architecture.
IA64's no integer multiply comes from HP-PA,
so is the Shift-Left-and-Add instructions.
Even the instruction encoding within the groups are
the same as HP-PA RISC.
IA64 = HP PA RISC instructions/encoding +
VLIW/EPIC concepts/ideas +
x86 emulation