so Jobs gets screwed by IBM over game consoles, thus Apple-Intel ?

[James Arveson]

Read it again, he's talking about P-M's not P4-M's. Totally different
architectures.

Correct. I meant the P-M Centrino.

You're misunderstanding the meaning of "coming into full production at
90nm". Up until now, the mix of chips has been 130nm and 90nm. The 130nm
chips were the last of their production of K7 chips, which have now been
phased out completely. That's why it's now into full production on 90nm,
they are now only manufacturing K8 chips at 90nm. They used the same
lines for 130nm and 90nm, just like they used the same lines for 180nm
and 130nm previously. Their line is flexible enough to do that.

There is no such thing as a flexible line to manufacture two wafer sizes.
The equipment sets are completely different. For example a batch of 300 mm
wafers is much heavier than 200 mm wafers, and so the line has to be
completely equiped with a whole new handling system. They essentially ran
two factories under one roof.

James

You mean Intel's much /smaller/ flash business.

No. I mean Intel's larger (but not much larger) flash business. The loss of
market share to Intel is one reason that AMD decided to sell off the
business.

Yousuf Khan

James

 

[YKhan]

Correct. I meant the P-M Centrino.

Okay, understood.

There is no such thing as a flexible line to manufacture two wafer sizes.
The equipment sets are completely different. For example a batch of 300 mm
wafers is much heavier than 200 mm wafers, and so the line has to be
completely equiped with a whole new handling system. They essentially ran
two factories under one roof.

Who said anything about 300mm? They were running 130nm and 90nm on the
same 200mm wafers in this case. A lot of their equipment has adjustable
resolutions to allow both the higher and lower density processes to be
run simultaneously.

They won't have 300mm wafers till Fab 36 opens. Fab 36 will likely
start out at 65nm right off the bat, in early 2006. But they say they
could start it off at 90nm on 300mm wafers too if they need.

No. I mean Intel's larger (but not much larger) flash business. The loss of
market share to Intel is one reason that AMD decided to sell off the
business.

For the year 2004, Spansion was still the #1 NOR provider. There was a
single quarter in 2004 where Intel outsold Spansion, after some heavy
discounting going for marketshare. Intel made some heavy losses on that
flash business because of it, but it dragged Spansion down with it too,
which was the goal. AMD is basically just spinning off Spansion so that
its earnings don't show up against its own. It'll retain a controlling
interest it seems. After Spansion is spun off, it'll become less of a
target for Intel.

Yousuf Khan

 

[Nate Edel]

Read it again, he's talking about P-M's not P4-M's. Totally different
architectures.

True... though I can't see any evidence of a shortage of 2.0/2.13ghz P-Ms at
first-tier companies (or Dell, which isn't really, but gets Intel chips like
it was first tier++). The price premium for the 2.13 is currently highway
robbery, but that's true of pretty much all top-of-the-line chips.

 

[Nate Edel]

It is fact - Intel has serious heat problems with their top-end CPUs; AMD
doesn't. You can look up any of the Web sites which do benchmarks - the
infamous THG even had to re-hash their recent long-term stability tests,
with restarts, so as not to make the Intel chips look too bad. This is all
common fact. You could also buy an Athlon64 system and check it out for
yourself.:-[]

Certainly true of Intel's new desktop chips since Prescott came out; I
haven't seen any evidence on THG or elsewhere that it's true at all for any
of the 2 1/2 generations of Pentium-M chips, even at the highest speed
ratings. I have yet to see anything comparable from AMD, in fact, though
I've get to take the time to track down full reviews of any Turion-based
laptops.

Geez I hope you didn't buy a 2.0GHz P4-M but a P-M (Pentium M)... often
known by the rabble as a Centrino.

Specs available online seem to indicate that the M3 is using the current
generation (2mb cache, 533mhz fsb) of Pentium M, not any sort of P4. I'm
fairly sure the P4-M is long gone from the market - replaced with the P-M
and the repackaged desktop "Mobile P4."

200Mhz in today's CPUs make hardly any difference in the same architecture
- across architectures it's hard to tell but, though I've never owned one,
it had always been my impression that clock for clock, a PowerPC would
thrash any x86.

Totally depends on which generation of PowerPC, and which generation of
x86... and which benchmark/workload you're talking about. x86 has never
been superb at cranking floating point, improvements in vector FP since the
P4 (and some improvement in non-vector with x86-64) notwithstanding, while
the PowerPC has generally been quite strong in this area.

At the same time, branch and integer performance has always been a lot
closer, and IIRC there's been a lot of lag on bringing Macs in particular up
to the latest memory performance and then FSB speeds - stuck on FPM memory
when the Pentium had already gone to EDO, a bit later to adopt SDRAM, a bit
later to adopt faster FSB speeds, a bit later to adopt DDR. Which hurts a
good bit.

Of course, P4 changed a lot of the rules, and clock-for-clock jumped a
generation or two back. On the other hand, a ~50% clock speed advantage and
more memory bandwidth makes up for a lot, if you don't care about power and
heat.

 

[Bill Davidsen]

Not in the least. Cache transistors damn near always come with
redundant blocks. the same is rarely true for logic transistors.
Also, my understanding of it is that the fairly even and structured
nature of cache allows for generally lower defect rates in that part
of the die.

Didn't Intel at one time have a CPU available with 256k or 512k of
cache, and the low cache size was one half or the other of the full size
cache, selected with fusable links?

From memory, feel free to do a refresh.

 

[Bill Davidsen]

in message


How does one tell whether one process is "more advanced" than another?
Higher yield? Faster, lower power transistors? fewer mask steps? Or press
releases?

Don't forget leakage. Doesn't matter how small or fast it would be if it
didn't melt. I think that's the next area for a breakthrough.

 

[TravelinMan]

Didn't Intel at one time have a CPU available with 256k or 512k of
cache, and the low cache size was one half or the other of the full size
cache, selected with fusable links?

From memory, feel free to do a refresh.

I seem to remember something like that with the Pentium Pro.

 

[Bill Davidsen]

Strange. I just bought a Toshiba Tecra M3 with a 2 GHz P4-M. They didn't
have any trouble delivering it.

The most common P-M notebook runs at



Jobs clearly stated that a G4 running at 1.6Ghz wasn't competitive with a
P4-M running at 1.8 GHz.

I don't know if you don't understand that the P-M and P4-M are totally
different chips, or simply were a bit confusing with your reply. The
fact that you got delivery of a laptop running a P4-M CPU doesn't seem
related to the previous paragraph you quote.

On the other hand, that paragraph says the P-M are running hot, and
there was a link posted here last week on O/C the P-M from 1.5 to 2.1 or
so which showed the power use to be minimally increased with clock, and
that the CPU ran up without voltage changes. I did bookmark that but on
another system. I believe it was on tomshardware but if someone wants to
add the correct link to this I won't have the link before next
weekend, it's on a computer I left back home.

I would say your 2.6GHz clock estimate is in agreement with mine, which
doesn't make either of us right ;-) But I would expect Apple to use a
dual core at slightly lower speed with some advanced power management if
they can. And I believe they can, although it might not ship for another
year or so (2008?).

 

[keith]

James Arveson wrote:

Don't forget leakage. Doesn't matter how small or fast it would be if it
didn't melt. I think that's the next area for a breakthrough.

Many wish for such. Only time will tell if the applied-physics is wrong.

 

[Tony Hill]

I was speaking more to the track record. As you pointed out to me, AMD has
just finally completed their conversion of Fab 20 to 90 nm, As it is only a
200 mm fab, the are still behind Intel (and much of the rest of the industry
leaders). Perhaps AMD will be able to make up some of this lag with their
new Fab, but that is a hope for the future, not the present.

I think you're really overestimating the rest of the industry,
particularly in regard to shipping high-performance microprocessors.
The very first 90nm products starting shipping about 2 years ago and
companies producing high-end chips didn't really start until late
2003/early 2004, right around the time that AMD starting producing
their first 90nm chips. They are about 4-6 months behind the leaders,
but that's it.

As to 65 nm, Intel claims to have been busy characterizing that process
since late 2003.
http://www.itnews.com.au/newsstory.aspx?CIaNID=17324

Characterizing a process is a LONG way from even starting test runs of
wafers, let alone actual production. Intel will have, at best, VERY
limited 65nm production this year, just like everyone else. If the
transition from 130nm to 90nm is any indication than it could be well
into next year before we start seeing meaningful volume of 65nm
production from any company.

And I thought that their fab wasn't completely converted until recently.
There is a common confusion between first shipped and high volume
production. When a fab is pushing a full volume of wafers through the line,
at targeted yields, then HVP has been achieved.

There's also a difference between pushing a high volume of wafers
through the line and pushing ONLY a particular type of wafers through
the line. The conversion doesn't happen overnight at ANY plant.
Typically the cross-over from one process generation to the next takes
a good 6-12 months. AMD is no different than any other company here.

And still running only 200 mm. There IS a difference between a 200 and 300
mm line - about 2X

200mm vs. 300mm wafers should have almost no impact on how long it
takes to transition from one process generation to the next. You
still have the same number of machines to replace, the same sort of
equipment to re-tune, all the same sorts of optimizations to make
before really ramping up production. The real difference comes in
your end result where you get twice as many dies when all is said and
done.

 

[Tony Hill]

There is no such thing as a flexible line to manufacture two wafer sizes.
The equipment sets are completely different. For example a batch of 300 mm
wafers is much heavier than 200 mm wafers, and so the line has to be
completely equiped with a whole new handling system. They essentially ran
two factories under one roof.

Uhh, are you really confusing the issue intentionally here? Who said
anything at all about 200mm wafer vs. 300mm wafers in the same plant?
The issue in question was the switchover from 130nm production to 90nm
production! While you're correct that it's not really practical to
have both 200mm and 300mm wafers in the same building, you most
definitely can (and *EVERYONE* does) run two different process
generations at the same time in the same building.

No. I mean Intel's larger (but not much larger) flash business. The loss of
market share to Intel is one reason that AMD decided to sell off the
business.

Intel and AMD have been trading off between being the #1 company in
flash for the past few years. They have pretty consistently being
within a few percentage points of one another in marketshare. For
most of 2004 AMD was the leader, but Intel slashed prices (apparently
by fairly substantial amounts) towards the end of the year to gain
marketshare. They are still fairly close.

Neither of them have been particularly profitable in their endeavors
to sell Flash memory. AMD has struggled to break even and only made
money on flash about one out of every 3 or 4 quarters. Intel used to
consistently lose money on their division that sold flash memory until
they rejigged their business divisions to group flash alongside their
mobile x86 processors and chipsets. Now it's much harder to pick out
just which division is making money and which is losing, but they are
showing a rather direct correlation between their mobile processor
revenue and income from this division, suggesting that flash isn't
contributing much (if anything) in the way of black ink.

 

[Tony Hill]

Didn't Intel at one time have a CPU available with 256k or 512k of
cache, and the low cache size was one half or the other of the full size
cache, selected with fusable links?

Intel not only used to have chips like that, they still do. This is
exactly how their Celeron processors start their life. I don't know
about their current Prescott/Celeron D chips, but the previous
generation of Northwood P4/Celeron chips had identical dies. The P4
chips had 512KB of cache, Celerons had 128KB of cache. Current
Pentium-M and Celeron-M chips share a similar heritage. Previously
they had PIII processors with 512KB of cache and Celerons with 256KB
of cache, while prior to that the PIII had 256KB and the Celeron
128KB. The original dies in each of these pairs were usually
(always?) the same, just different amounts of cache enabled/disabled.

However even in the larger-cache chips there is redundancy built in.
Eg the new P4 600 series with 2MB of L2 cache has more than just 2MB
of cache on the die.

 

[George Macdonald]

It is fact - Intel has serious heat problems with their top-end CPUs; AMD
doesn't. You can look up any of the Web sites which do benchmarks - the
infamous THG even had to re-hash their recent long-term stability tests,
with restarts, so as not to make the Intel chips look too bad. This is all
common fact. You could also buy an Athlon64 system and check it out for
yourself.:-[]

Certainly true of Intel's new desktop chips since Prescott came out; I
haven't seen any evidence on THG or elsewhere that it's true at all for any
of the 2 1/2 generations of Pentium-M chips, even at the highest speed
ratings. I have yet to see anything comparable from AMD, in fact, though
I've get to take the time to track down full reviews of any Turion-based
laptops.

Intel had almost the same delay on Dothan as they had on Precott for the
same basic resons. A P-M running at full tilt runs *hot*, though that does
not happen that often. As for the Athlon64, at 90nm it runs extremely cool
and has power management which is excellent; AMD would not have had to do
much to it to get Turion power management on a par with P-M, other than
peak wattage... the Athlon64 is almost there anyway.

Specs available online seem to indicate that the M3 is using the current
generation (2mb cache, 533mhz fsb) of Pentium M, not any sort of P4. I'm
fairly sure the P4-M is long gone from the market - replaced with the P-M
and the repackaged desktop "Mobile P4."

Right - my point. He doesn't even know which Intel chip Apple is talking
about.

Totally depends on which generation of PowerPC, and which generation of
x86... and which benchmark/workload you're talking about. x86 has never
been superb at cranking floating point, improvements in vector FP since the
P4 (and some improvement in non-vector with x86-64) notwithstanding, while
the PowerPC has generally been quite strong in this area.

Calling SSE(?) "vector" is a bit of a stretch - no?

At the same time, branch and integer performance has always been a lot
closer, and IIRC there's been a lot of lag on bringing Macs in particular up
to the latest memory performance and then FSB speeds - stuck on FPM memory
when the Pentium had already gone to EDO, a bit later to adopt SDRAM, a bit
later to adopt faster FSB speeds, a bit later to adopt DDR. Which hurts a
good bit.

Of course, P4 changed a lot of the rules, and clock-for-clock jumped a
generation or two back. On the other hand, a ~50% clock speed advantage and
more memory bandwidth makes up for a lot, if you don't care about power and
heat.

Like I said, I've never owned a PowerPC so would not know hard numbers.

 

[Robert Myers]

On Tue, 05 Jul 2005 11:27:29 -0700, (e-mail address removed) (Nate Edel) wrote:

A P-M running at full tilt runs *hot*, though that does
not happen that often. As for the Athlon64, at 90nm it runs extremely cool
and has power management which is excellent; AMD would not have had to do
much to it to get Turion power management on a par with P-M, other than
peak wattage... the Athlon64 is almost there anyway.

Does anyone know of data that would illuminate whatever process (as
opposed to microarchitectural, circuit design, or just plain BS)
advantages AMD may have?

Calling SSE(?) "vector" is a bit of a stretch - no?

"SSE or SSE2 vector" hits 1680 times on google groups. I'd call it
short vector arithmetic, but that's gilding the lily, I suppose.

RM

 

[George Macdonald]

Does anyone know of data that would illuminate whatever process (as
opposed to microarchitectural, circuit design, or just plain BS)
advantages AMD may have?

They took up Cu/SOI early in the game... and had to change horses to get it
done. As I've also been pointing out (did you not read the thread?) Dual
Stress Liner is supposed to be more advanced than strained silicon though
it's not clear to what extent Intel may be using a similar concept with
their differential strained silicon. The results of AMD's latest process,
as I've harped on about, are pretty clear in terms of performance/W:
http://www.lostcircuits.com/cpu/amd_venice/11.shtml

"SSE or SSE2 vector" hits 1680 times on google groups. I'd call it
short vector arithmetic, but that's gilding the lily, I suppose.

WRT to Apple, I guess the question here is are we going to see a SSE4 which
matches Altivec, which is itself a bit of a "stretch" as a "vector" unit?

 

[Robert Myers]

They took up Cu/SOI early in the game... and had to change horses to get it
done. As I've also been pointing out (did you not read the thread?) Dual
Stress Liner is supposed to be more advanced than strained silicon though
it's not clear to what extent Intel may be using a similar concept with
their differential strained silicon. The results of AMD's latest process,
as I've harped on about, are pretty clear in terms of performance/W:
http://www.lostcircuits.com/cpu/amd_venice/11.shtml

The link doesn't seem to work, and it don't think it would answer the
question I was asking, anyway. I don't know my way well enough around
the fundamental literature of process technology to know what might be
published, but I was hoping for something that would illuminate the
differences in the processes at the device level.

RM

 

[George Macdonald]

The link doesn't seem to work, and it don't think it would answer the
question I was asking, anyway. I don't know my way well enough around
the fundamental literature of process technology to know what might be
published, but I was hoping for something that would illuminate the
differences in the processes at the device level.

The link works for me.

 

[Del Cecchi]

The link doesn't seem to work, and it don't think it would answer the
question I was asking, anyway. I don't know my way well enough around
the fundamental literature of process technology to know what might be
published, but I was hoping for something that would illuminate the
differences in the processes at the device level.

RM

Probably some articles in the digest of ISSCC, or maybe the Internation
Electron Devices Meeting, or at a little more layman level,
Microprocessor Report.

There are apparently, according to George, two things. SOI (Silicon on
Insulator) vrs Bulk. In the AMD process the area that is not transistors
is made to be SiO2. In the Intel process it is bulk Si of an appropriate
doping. SOI is generally thought to have lower capacitance for devices
and lower layers of wire.

Strained Silicon... CMOS uses both holes and electrons as carriers of
current. The speed at which they move is called mobility. Straining the
silicon in one way, compression or tension I forget which is which, makes
electrons move faster and holes move slower. Good for NFET bad for PFET.
Straining it the other way makes electrons slower and holes faster Good
for PFET bad for NFET. It may be that Intel only has one kind of strain
and AMD has both.

del cecchi