SiS doesn't think AMD's integrated memory controller is a good idea

[David Wang]

Seems to me like Intel does NOT have any plans for an integrated
memory controller. In fact, that whole article is just more people
echoing what we've all been saying in this newsgroup for a little bit,
that sooner or later Intel HAS to integrate their memory controller if
they want to remain at all competitive. Still, in this article they
continue to sound like they're in denial. 4 cores off a front-side
bus design?! One only needs to look at just how poorly the 4
processor Xeon performs relative to the Opteron to realize that the
above-mention "Intel senior fellow" is smoking some wacky stuff.

4P Xeon's on the same FSB loads down the interconnect, and that limits
the datarate. 4P Xeon's are running at 400 Mbps while their 1P desktop
brethen are cranking at 800 Mbps going to 1066 Mbps. It would seem that
there is a significant bandwidth differential between the 4P/4S (4
processor, 4 socket) config and the 4P/1S config.

 

[Yousuf Khan]

A Usenet Message ID - if your newsreader doesn't support it, sorry... but
you can plug it in at Google Groups.

Just plugged it into Google Groups, and it just came up with this exact
same message with that message id in the body. Why not just post a
Google Groups link to the message?

Yousuf Khan

 

[alexi]

He may have a small point. Lots of devices (esp AGP vidcards)
do BM-DMA. They're going to experience increased latency
going through the CPU integral MC. But that's probably better
than the CPU suffering the latency with a traditional Northbridge.

Why would you think so? The bus-master traffic has to be snooped
and snarfed anyway. In architectures with FSB is it done via
slow FSB, but with integrated MC it surely can be done faster.
Therefore, SiS has no point except that they might be hinting on some
general deficiency of AMD controllers, say, limited support for bigger
memory capacity, drive strength, future speeds, or newer memory
types.

- aap

 

[George Macdonald]

Just plugged it into Google Groups, and it just came up with this exact
same message with that message id in the body. Why not just post a
Google Groups link to the message?

It *is* a Google Groups "link". No not as a search string - in Google
Advanced Groups Search, paste it into the Message ID box. I haven't even
looked at Thunderbird yet but Free Agent can use it directly within its own
message list.

If you must, here's the resulting msg:
http://groups-beta.google.com/[email protected]&lr=&hl=en

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??

 

[George Macdonald]

Why would you think so? The bus-master traffic has to be snooped
and snarfed anyway.

It *is* an interesting question. There is bound to be some latency from
Hypertransport packet processing and the quoted 4GB/s (on the latest 1GHz
versions) each way seems to ignore that - latency figures would be nice.
AGP traffic doesn't have to be snooped, not the bulk transfer stuff anyway,
and it's 2.1GB/s peak rate is well within HT's capacity. I'm not sure how
PCI-Express sits here with packet disassembly/reassembly between the two
and the peak rate for both at 4GB/s but for the data phase, Intel's MCH
would have to be faster in general for PCI-Express bulk video data... I'd
think. I assume that the 16-lane PCI-Express video data doesn't have to be
snooped?

In architectures with FSB is it done via
slow FSB, but with integrated MC it surely can be done faster.
Therefore, SiS has no point except that they might be hinting on some
general deficiency of AMD controllers, say, limited support for bigger
memory capacity, drive strength, future speeds, or newer memory
types.

The only thing I've seen is that the 2T timing which AMD suggests for large
memory seems to have quite a drastic effect on bandwidth - "non-scientific"
observation of a drop of ~1GB/s on socket 939 systems.

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??