AIUI, in that PCI-Express is not a bus at all - more several point to point
interconnects - I suppose it is a swing away.
I can intuit what you mean, but can't quite grasp the difference
between several interconnects and a bus. I presume it means that
traffic on the same wires (I assume they are the same wires?) is
mediated in a different way or at a different level?
The idea is that video will have a fat pipe (16-lane) within PCI-Ex
specs; most regular devices will have a 1-lane version and if
necessary, down the road some high bandwidth
devices may get more lanes as required.
Now I get it! It's that other devices are now crowding PCI into
obselescence, e.g. Giga-LAN, S-ATA etc. so instead of AGP + PCI slots,
we need at least 3 x fast slots. PCI-Ex sounds better designed to
handle this gracefully, i.e. allocate width as needed without having
to shatter old standards and set new ones (as AGP ?x now does)
Ultimately, it shakes out to:
- the highest CPU clock the CPU('s cache) can handle
- the highest RAM clock the current RAM standard can handle
- a high standard for bits that have to be in the case (PCI Ex?)
- a standard for bits that have to be outside the case (USB?)
- a standard for bits that are wire-less
The trend will be to either toss stuff out of the case (so that dumb
retail can sell them safely) or build it into the mobo, and ultimately
processor core, as Moore's Law allows. Perhaps at some stage we won't
have the "has to be inside the case for speed" layer at all.
For video, it *is* also a break, I suppose, in that it's not a mezzanine
bus but that term is getting to have less meaning in modern systems.
In the original VL-Bus vs. PCI sense, I doubt if we will ever see a
"local bus" again, given how RAM out-paces other cards and devices.
In what sense is PCI Ex not a mezzanine bus?
PCI-Express is less accessible as a standard to mere mortals, so I'm not
sure what design parameters there are available for the implementers but it
would also appear that having a bi-directional high bandwidth inter-connect
for video is a bit of a waste.
Unless they foresee the GPU as generating system input in some way?
At any rate it's here and going at full steam ahead - Intel finally got its
way on NGIO.
As for AGP, the DIME seems to have been a red herring and
and with the strobe clocks running at quadruple the common clock for 8x, it
was pretty much tapped out on future directions.
Yep. I only understand the last bit about AGP clock; also thinking
that whenever they up the data rate, they have to drop voltage to stop
the wires frying, and I'm wondering at what point VR will be too
granular to maintain voltage consistency.
So does PCI Ex solve this by adding more physical wires? That's
interesting if so, given the original "parallel for data speed"
approach that swung to the "serial to avoid cross-talk and reduce pin
count" phase we are currently enjoying with S-ATA and USB.
Thinking back on it (especially the initial rocky and costly rollout),
PCI's been a pretty good bus. It gained traction here in around 1995,
so it's served us for 10 years - ?as long as ISA-16.
And yet it seems that VIA still couldn't get the hang of it, as
recently as a few years back (the UIDE corruption scandal).
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