Sure there is -- SRAM and other designs which take more xtors
per cell. With the continually decreasing marginal cost
of xtors and a shortage of useful things to do with them,
I expect this transition to happen at some point.
SRAM could shave off 15 ns in the case of DRAM page miss. Or 50-55ns
in the case of page conflict, but those are very rare. In the
supposedly most common case of DRAM page hit SRAM doesn't help at all.
Actually, you will have hard time finding commodity SRAMs that is as
fast as now common DDR2-800 CL5 at page hit.
Another potential saving with SRAM comes from the fact that memory
controller is simpler. Don't know how much it could bring. The likes
of Opteron and Power6 run their MCs at very high speed so I'd guess it
would be hard to shave off more than 1-2 ns here.
Now look at the flop side:
1. Pins - SRAM address bus is up to twice wider than the DRAM. You can
construct SRAM with pseudo-pages and multiplexed address bus, but then
you give up on part of the latency advantage.
2. Capacity. The big one. SRAM capacity lags behind DRAM by factor of
5-10. It means that you will either need more channels (expensive
motherboard, expensive packaging of MPU/NB; not always possible due to
mechanical constrains) or more DIMMs per channel. The later noramally
means more buffering = higher latency. For example, for DDR2-667 one
can put on one channel 2 unbuffered DIMMs (lowest latency), 4
registered DIMMs (medium latency) or up to 8 fully-buffered DIMMs (the
highest latency).
3. Power consumption. I'm not an expert in this area, but according to
my understanding under heavy load SRAM consumes 2-3 times more power
than the equivalent DRAM. That's partly compensated by lower idle
power consumption (no need for refresh).
4. Cost. That's the other unfortunate effect of lower capacity.
