In alt.comp.hardware.pc-homebuilt
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I was mistaken, it seems. I thought the logic on the ECC-capable boards
were done logically and transparently; auto-correcting on-the-fly, like
I would have done; the corrected-read *always* appearing on the output.
However, it seems that would slow the delivery of memory-results down by
at least a gate-delay or two; and speed-is-all in today's computers.
Besides, as-pointed-out by others in this discussion, today's memories
are actually pretty damned good; and memory-failures are rare enough (at
the most a few times a day; and at the least almost never) that it
doesn't pay to invoke that extra delay. So, while the logic *is* on the
DIMM, the end-result is just to raise an interrupt if an error occurs;
and then back-up and correct the error afterwards. (Hopefully it didn't
cause something disastrous to happen when it occurred.) I'm not too
sure how you CAN correct a memory-error after it already happened, even
if you know what the error was (and that's what ECC does). But
supposedly they can.
OR, maybe I'm mistaken; and the ECC memory *does* correct it on-the-fly;
and just raises an exception to let the system know that a correction
was made. I'd have to look into the specifications I guess.
In any case, the interrupt *does* allow the system to log errors so you
know when things are going down the tubes; and unlike parity-errors,
which don't do you a bit of good, with ECC the errors *are* corrected.
That's what the middle 'C' in ECC stands for.
You didn't look closely enough.
They have several extra chips.
Both extra memory bits, *AND* extra logic.
