Processor Speed

[Del Cecchi]

Maybe. I wasn't in on the Power4's politics. However, it surely
didn't end up as a "straightforward core". Five instructions
issued/completed per cycle and a couple of hundred instructions in
flight isn't exactly "straightforward". Sure, more cache would
have been nice, but the second core was nicer. Apparently they
traded off "straightforward" and larger caches for better
performance. Ok, I'll accept that that's not the same as adding
another core because it "was something to do with transistors". I
maintain that they would have improved single-core perforamnce with
those transistors (apparently they did that too), were that
possible.

It was a long time ago, and I don't know the final result, but I think
the question was perhaps in-order vrs out of order, with a mere
superscalar being considered straightforward.

Adding transistors to the core to make it even more complicated and have
better performance was considered too risky, or so the story went. The
issue wasn't really the transistors but the complication and schedule.

del

 

[Keith]

It was a long time ago, and I don't know the final result, but I think
the question was perhaps in-order vrs out of order, with a mere
superscalar being considered straightforward.

Well, the Power4 is about as SS and OoO as you can get (damned near
every resource is renamed). Are you *sure* you're remebering the
Power4?

Adding transistors to the core to make it even more complicated and have
better performance was considered too risky, or so the story went. The
issue wasn't really the transistors but the complication and schedule.

Again, this doesn't sound like Power4 history. No transistors were
spared in there. ;-) ...well there are some funky dispatch rules,
but...

 

[Del Cecchi]

Well, the Power4 is about as SS and OoO as you can get (damned near
every resource is renamed). Are you *sure* you're remebering the
Power4?




Again, this doesn't sound like Power4 history. No transistors were
spared in there. ;-) ...well there are some funky dispatch rules,
but...

There was some story that convinced the powers that be that THIS time
they would actually make a processor that worked, after all of the
failures dating back to the PowerSingleChip episode. As an AS400 guy
before, during and after the transition from IMPI to PowerPC I got to
see the whole thing.

What would you have used as a story why "This Time it's Different"?

 

[Keith]

There was some story that convinced the powers that be that THIS time
they would actually make a processor that worked, after all of the
failures dating back to the PowerSingleChip episode. As an AS400 guy
before, during and after the transition from IMPI to PowerPC I got to
see the whole thing.

That's one I hadn't heard, and the microarchitecture certainly
doesn't match the attitude. ...but then again, I've just recently
been assimilated.

What would you have used as a story why "This Time it's Different"?

"You don't have another option."

 

[Del Cecchi]

That's one I hadn't heard, and the microarchitecture certainly
doesn't match the attitude. ...but then again, I've just recently
been assimilated.




"You don't have another option."

You could could have gotten on I35 and driven north about 20 hours, take
a right on I90, go north on US63 to Hiway52N and there you are.
Northstar, Pulsar, etc were already done. Proven track record.
Multithreaded cpus, with cost effective use of latest technologies.
Farmers on the tundra.


del cecchi

 

[Keith]

You could could have gotten on I35 and driven north about 20 hours, take

Me? If I drove north for 20 hours I'd be in the tundra, alright.
....there wouldn't be any farmers around though. ;-)

a right on I90, go north on US63 to Hiway52N and there you are.
Northstar, Pulsar, etc were already done. Proven track record.

Istar (I think that was the name) was a different kettle though,
AIUI.

Multithreaded cpus, with cost effective use of latest technologies.
Farmers on the tundra.

Wrong division. You don't see the midwest farmer's daughters
making Zs, do you? ;-)

 

[Del Cecchi]

Me? If I drove north for 20 hours I'd be in the tundra, alright.
....there wouldn't be any farmers around though. ;-)

I was talking about starting in Austin. Unclear of me.

Istar (I think that was the name) was a different kettle though,
AIUI.

All one family, same team. AIUI??

Wrong division. You don't see the midwest farmer's daughters
making Zs, do you? ;-)

The stars were all multithreaded, although some nitpickers say it was
merely coarse multithreading, switch on whatever.

Nope, no Z's. POK and Boeb. got that bidness sewed up. We all hired
guns pretty much now days.

 

[Keith]

I was talking about starting in Austin. Unclear of me.

I knew that, but was just twitting you. I35 alone is 20hrs from
here. ;-)

All one family, same team. AIUI??

I can't remember the name (IStar sounded a little to much like a
product). The one I was thinking about was a research project into
SOI ("Glacier" was our end of that disaster ;-).

The stars were all multithreaded, although some nitpickers say it was
merely coarse multithreading, switch on whatever.

Merely? Intel doesn't do what I'd call fine-grained either (only
issue/complete from one thread at a time, AIUI). Did the *s
require a flush inbetween too (i.e. no instructions from the other
thread in the pipe)?

Nope, no Z's. POK and Boeb. got that bidness sewed up.

Up to now, at least.

We all hired guns pretty much now days.

Yeah, I've noticed that. Too bad.

 

[Del Cecchi]

I knew that, but was just twitting you. I35 alone is 20hrs from
here. ;-)




I can't remember the name (IStar sounded a little to much like a
product). The one I was thinking about was a research project into
SOI ("Glacier" was our end of that disaster ;-).

As I recall, glacier was the "risc" that rochester was proposing/had
started on as the next gen AS400 before the decree came down from the
clouds that all the world shall be PowerPC. That would have been in the
pre SOI days. But it was coming.

Istar really was a product.

Merely? Intel doesn't do what I'd call fine-grained either (only
issue/complete from one thread at a time, AIUI). Did the *s
require a flush inbetween too (i.e. no instructions from the other
thread in the pipe)?

I don't know. but stars had pretty short pipes so it shouldn't have
been too much of a hit.

Up to now, at least.




Yeah, I've noticed that. Too bad.

Sort of fun actually. MD and servers use our services. Why buy a cow
and all that. Rent, don't buy.

 

[David Kanter]

I was talking about starting in Austin. Unclear of me.

I knew that, but was just twitting you. I35 alone is 20hrs from
here. ;-)

Where is 'here' for you keith?

I can't remember the name (IStar sounded a little to much like a
product). The one I was thinking about was a research project into
SOI ("Glacier" was our end of that disaster ;-).


Merely? Intel doesn't do what I'd call fine-grained either (only
issue/complete from one thread at a time, AIUI). Did the *s
require a flush inbetween too (i.e. no instructions from the other
thread in the pipe)?

You'll have to forgive me for interrupting, as I'm not an IBMer, but I
have talked a bit with John Borkenhagen, who was big on the threaded
*stars. IIRC, they kept the core simple enough that the switch latency
was 1-2 cycles (i.e. 0-1 dead cycles). Current SoEMT chips have longer
times due to increased complexity (I'm thinking of the SPARC64s and
Montecito).

Up to now, at least.

Upto POWER6 : P

What is Boeb?

David

 

[Keith]

Where is 'here' for you keith?

Burlington Vermont (was in P'ok before the great implosion)

You'll have to forgive me for interrupting, as I'm not an IBMer, but I

No forgiveness needed. It's a puplic forum; wade on in.

have talked a bit with John Borkenhagen, who was big on the threaded
*stars. IIRC, they kept the core simple enough that the switch latency
was 1-2 cycles (i.e. 0-1 dead cycles). Current SoEMT chips have longer
times due to increased complexity (I'm thinking of the SPARC64s and
Montecito).

That makes sense, but I'd think the simplicity would be more in the
OoO hardware, rather than thread switching (maybe the same thing).
But that's just a guess since I don't know the *stars
microarchitecture at all. ...only what I've read on comp.arch. ;-)

Upto POWER6 : P

Add Austin.

What is Boeb?

Boeblingen Labs, Germany

 

[Del Cecchi]

Burlington Vermont (was in P'ok before the great implosion)


No forgiveness needed. It's a puplic forum; wade on in.


That makes sense, but I'd think the simplicity would be more in the
OoO hardware, rather than thread switching (maybe the same thing).
But that's just a guess since I don't know the *stars
microarchitecture at all. ...only what I've read on comp.arch. ;-)

I wonder how hard it would be to get the design documentation made
public. I bet the chip vhdl is still around somewhere. And the
simulation models.

 

[Keith]

I wonder how hard it would be to get the design documentation made
public. I bet the chip vhdl is still around somewhere. And the
simulation models.

Shirley you jest!