J
Jim Brooks
Signs and portents as JMS would say.
Stevel Jobs does a 180' and enthusiastically becomes
Intel's bedfellow on the basis of a compelling roadmap.
That roadmap has to be pretty darned interesting.
Intel claims they aren't developing Hyperthreading anymore.
But Intel now knows all the issues involved in hw threading.
Why not exploit that know-how as an advantage over AMD?
AMD has only a fraction of the resources that Intel has,
so AMD will have a hard time catching up
My speculation is that Intel will build on their HyperThread experience
to design a "parallel x86". x86 CPUs have become superscalar machines.
The next evolutionary step is a parallel machine. Dual-cores are only
an inefficient stop-gap design that wastes transistors with duplicated
or unnecessary resources (eg coherency logic between the core's caches).
My ideas for a parallel x86:
- thread quantums
The idea is to move coarse-granularity timer-driven time-slicing
into the hw so that time-slices can be instruction-granular.
- thread prioritization
The OS assigns static priorities to threads.
The hw computes dynamic priorites according to static priority
and instruction issue for a thread per quantum.
- sub-threads
Support for parallel programming.
A reduced 80386 Task-State Segment (TSS) will be defined
(avoid saving unnecessary registers such as ES/FS/GS)
A variant of JUMP [TSS] with a new Thread bit defined in the TSS
will spawn a sub-thread (analoguous to a UNIX child process).
The sub-thread can stop by IRET [TSS].
A new WAIT [TSS] will synchronize the parent with its sub-thread.
- thread exceptions
A thread can raise exceptions to end or suspend itself.
- cache lines have thread bits in addition to LRU bits
When one cache line has to be evicted, victimize the line owned
by a lower-priorty thread.
- ALUs: 8 simple, 4 complex.
- FPUs: 4 FADD, 4 FMUL, 2 FLDST.
- deprecation of FP SIMD instruction set
SIMD was a good idea for a single-thread CPU as it let the control unit
issue a single-instruction for multiple-data without resource hazards.
But a multi-threaded control unit would function optimally with
a wide window of decomposed (SISD) instructions.
Stevel Jobs does a 180' and enthusiastically becomes
Intel's bedfellow on the basis of a compelling roadmap.
That roadmap has to be pretty darned interesting.
Intel claims they aren't developing Hyperthreading anymore.
But Intel now knows all the issues involved in hw threading.
Why not exploit that know-how as an advantage over AMD?
AMD has only a fraction of the resources that Intel has,
so AMD will have a hard time catching up
My speculation is that Intel will build on their HyperThread experience
to design a "parallel x86". x86 CPUs have become superscalar machines.
The next evolutionary step is a parallel machine. Dual-cores are only
an inefficient stop-gap design that wastes transistors with duplicated
or unnecessary resources (eg coherency logic between the core's caches).
My ideas for a parallel x86:
- thread quantums
The idea is to move coarse-granularity timer-driven time-slicing
into the hw so that time-slices can be instruction-granular.
- thread prioritization
The OS assigns static priorities to threads.
The hw computes dynamic priorites according to static priority
and instruction issue for a thread per quantum.
- sub-threads
Support for parallel programming.
A reduced 80386 Task-State Segment (TSS) will be defined
(avoid saving unnecessary registers such as ES/FS/GS)
A variant of JUMP [TSS] with a new Thread bit defined in the TSS
will spawn a sub-thread (analoguous to a UNIX child process).
The sub-thread can stop by IRET [TSS].
A new WAIT [TSS] will synchronize the parent with its sub-thread.
- thread exceptions
A thread can raise exceptions to end or suspend itself.
- cache lines have thread bits in addition to LRU bits
When one cache line has to be evicted, victimize the line owned
by a lower-priorty thread.
- ALUs: 8 simple, 4 complex.
- FPUs: 4 FADD, 4 FMUL, 2 FLDST.
- deprecation of FP SIMD instruction set
SIMD was a good idea for a single-thread CPU as it let the control unit
issue a single-instruction for multiple-data without resource hazards.
But a multi-threaded control unit would function optimally with
a wide window of decomposed (SISD) instructions.