I've been looking for info on how the IDE interface works for
a while now, and I'm puzzled by why there isn't a web page
somewhere that does a decent job of explaining the low level
hardware operation. I started today's search here:
http://en.wikipedia.org/wiki/Advanced_Technology_Attachment
The only thing that caught my eye there, was the statement about
"The master drive arbitrates access to devices on the channel".
I haven't seen any other technical references to this arbitration
function, and if there is such a function, it would be important
to understand how it works.
This guide contains more practical advice. It stretches for several
pages.
http://www.storagereview.com/guide2000/ref/hdd/if/ide/confJumpering.html
Whether you are using cable_select for the two drives, or are
over-riding the cable_select function by setting the drives
to master and slave explicitly, the results are the same. Each
device is being given a static unchanging logic value of 0 or 1.
The device uses that to recognize when a command is addressed to it.
Thus, there is no speed advantage to either scheme. Cable_select
applies the logic 0 or logic 1 to a pin on the drive's IDE connector.
The master or slave jumpers apply the logic level when a jumper
is installed.
To find out about the most basic of operations, I looked at
the datasheet for the Southbridge of the 440BX chipset. This
would be back in the era when bus mastering was invented, so
I was hoping they wouldn't be as bashful about explaining
how IDE works.
It seems the two CS signals on the cable are not used to
address the two disks individually. In fact, those two
signals address both disks at the same time. Each disk
has a block of control registers and a block of commmand
registers. One CS signal talks to control registers, and
the other to the command registers. A CS signal is seen by
both drives, and the registers in both drives are written
at the same time. The drive compares the drive number written
in the drive/head register, to the master/slave value it was
given via cable_select or master/slave jumper. As far as I
can figure out, that is how a drive determines whether the
latest command is for it or not.
PDF page 193 of 440BX Southbridge:
http://developer.intel.com/design/intarch/datashts/290562.htm
In terms of one drive holding up another, I found this
document in a search. It seems this made it into the
standards. PDF page 18 shows how operations to the
disks may overlap - the implication is, that only the
data transfer phase represents a significant contention
between the drives - so you wouldn't be waiting 110ms for
the head on a CDROM drive to seek to a spot on the CD,
holding up a hard drive in the process.
http://www.t10.org/ftp/t10/document.95/95-301r0.pdf
In terms of standards, there are interim releases of the
standards (before they are official) on sites like this.
The first is Commands, the second is Transport Layer.
PDF pages 37 and 39 of the second document (d1532v2r1a),
have drawings of the 40 and 80 pin IDE cable.
http://www.t13.org
http://www.t13.org/docs2002/d1532v1r1a-ATA-ATAPI-7.pdf
http://www.t13.org/docs2002/d1532v2r1a-ATA-ATAPI-7.pdf
On the 80 wire cable, master (device 0) is shown on the end
of the cable. That is where it would be when using cable_select.
Master can be forced by using the drive jumpers. But, if you
had only a single drive, connected it to the middle connector,
and forced it to master, the system software would refuse to
use the fast ultra DMA transfer modes, because of the big
stub hanging off the end of the cable. That is why, with
the 80 wire cable, you fill the end position first, then
the middle connector. If both positions are filled, then
you can make either drive the master if you want. And
that kind of answers how you would handle a case of CDROM
on top and hard drive underneath. Just set the hard drive
to master, the CDROM to slave, and connect the CDROM to the
end of the cable.
Apparently, IDE timing is independent on the cable. That
means two drives may use different UDMA rates if they want,
without affecting one another. I didn't see anything permitting
the mixing of PIO and DMA on the same cable, but you wouldn't
want PIO polled mode in any case.
While I haven't explicitly answered your question, I hope
that gives you a few ideas about how flexible this stuff is.
Naturally, there will always be pieces of hardware that
defy the rules.
Paul