what's the truth behind the ddr400 memory compatibility?

  • Thread starter Thread starter Vin
  • Start date Start date
Why do some mobos full support (or nearly full) the ddr333 and not the
ddr400?

Vini
Click to expand...

Probably because the chipset on the board is older and wasn't made to
support DDR400 when it was released.

Ed
 
ok, but what about the mobos of today? they actually do not support all the
ddr400 memories! (i'm guessing for what i saw)

Is it the ddr400 now full supported (like the ddr333) for any mother of
asus?
 
ok, but what about the mobos of today? they actually do not support all the
ddr400 memories! (i'm guessing for what i saw)

Is it the ddr400 now full supported (like the ddr333) for any mother of
asus?
Click to expand...

Electrically, it is pretty hard to drive memory at DDR400
or higher (when multiple DIMMs are involved). If the only
job a Northbridge had to do, was drive the memories, the
design might be easier to achieve. The compromises come,
when other circuitry and interfaces are added to the Northbridge.
(For example, there are hardly any Northbridge chips with integrated
graphics cores that work properly. The 865GE might be the only
one of its generation. I haven't read too many reports about
current generation integrated graphics chips, with regard to
proper operation. ATI doesn't count, because their BIOS are
so screwed up.)

The same problems occur, even when the memory controller is
placed inside the processor, as is done in the Athlon64
family. They have problems driving DDR400 as well. (You have
to set Command Rate to 2T, to get them to work.)

In any case, the easiest driving task, is driving a single
stick of memory on a memory channel. It especially helps if
the DIMM is single sided (8 chips instead of 16 chips). None
of the trends that allow high memory speed, allow lots of
memory to be added to the computer.

DDR DIMMs have been run higher than DDR600, but never in
a four stick dual channel configuration. Similarly, don't
expect a three slot single channel motherboard to run
three sticks of memory at DDR400 rates.

One notable exception is the Nforce2 chipset. When you use
CAS2 DDR400 memory, you can run three sticks on there without
a problem. The trick in that case, is there are three separate
address busses (or so it is claimed) coming from the Nforce2
Northbridge. Using separate busses, means the load on each
interface is a single stick of RAM. That is why that load
can be successfully driven.

That kind of solution is seldom used on Northbridge chips.
To keep the price of a chipset low, you cannot let the pin count
on the bottom of the chip get too large. Basically, the price
is determined by the pin count, and not by the silicon itself.
That gives an incentive to not use multiple address/command
busses.

Intel has a development called FB or fully buffered memory. It
is a new form factor DIMM, where the chips don't directly
connect to the bus. Each DIMM has buffer chips, to decouple the
memory chips from the bus. A point to point connection is used
from the FB to the Northbridge. One advantage of this concept,
is no new kinds of memory need to be created. The buffer chip
must be custom designed for DDR and DDR2, so a different kind of
memory needs a different kind of buffer chip. Because the interface
is point to point from FB DIMM to Northbridge (the DIMMs do not
share a bus), there should be no issues with such a product
meeting its stated performance targets. As to when this will
be introduced into a commercial product, only time will tell.

http://www.theinquirer.net/?article=15167
http://www.theinquirer.net/?article=15189
http://www.theinquirer.net/?article=15214

As long as the current generation of motherboards uses shared
busses, where more than one electrical load is placed on the
bus at a time, there will be problems with loading and
compatibility. While this concept has kept the price of the
motherboard lower, it has not made the customer experience
a pleasant one.

Some day, all interconnect on the motherboard will be point to
point. The PCI bus was a shared bus, with many loads sitting
on the same bus lines. PCI Express, the replacement, uses point
to point unshared connections, from each PCI Express peripheral
chip, to the bridge that drives the bus lines. Engineers will
try to make all high speed interconnect that way, due to the
ease of design. Look at disk drives - previously we had two
drives sharing a ribbon cable, and now we have point to point
SATA interconnect to the motherboard. The Northbridge and
memory interfaces will be the last things to receive a
redesign.

Paul
 
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