Yousuf Khan said:
How fast can these things go anyways? In Z-RAM, it looks like they're
replacing a DRAM's capacitor with a /capacitive effect/ instead. Even
so, can any capacitor-based memory keep up with static ram? And wouldn't
they still need to go through a refresh cycle just like DRAM? I'm just
having trouble understanding how you can turn this into a cache ram.
There is nothing fundamental about SRAM or DRAM that makes one faster
than the other. They're both charge (storage) level based memory,
and the way you "read" data is to sense the value stored in the
cell. There's the additional trouble of having destructive reads for
the DRAM devices, but other than that, not a whole lot of difference.
You can optimize SRAM for density and DRAM for speed, but since SRAM
cells are much larger than DRAM cells, you can never get close to
DRAM density, so you always end up (somewhat) optimized for speed.
In (commodity) DRAM devices the opposite is true and pushed to the
extreme, so commodity DRAM devices are slow as molasses. There are
low latency DRAM devices, and IBM already offer all sorts of variants
of embedded DRAM blocks as part of its ASIC offerings, and those
embedded DRAM blocks are much larger (per bit) than their relatives in
commodity DRAM devices. Although part of the reason is that the
capacitive layers in the DRAM-optimized processes are specially
designed for it, while the embedded DRAM blocks have to use specially
inserted capacitive layers in the eDRAM process - suffering an area
penalty in the process, another part of the reason is that additional
logic elements are typically added to eDRAM to make them into SRAM-like
blocks.
IBM has been evangalizing eDRAM for eons now, and on more than one
technical forum, (a few presenters from) IBM argue that it would be
more cost effective for Intel to have used eDRAM as opposed to SRAM
for L3 cache. The argument was that for the same die size, the same
number of cells are hung on the bitlines, but since the cells are
smaller, the wires are shorter, thus ironically faster because of
smaller wire delay. The claim was that overall, a 6MB eDRAM L3 would
be far smaller than a 6 MB SRAM L3, while it would be just a fraction
of a hair smaller than SRAM. (Random cycle time is longer because
of write-back for the destructive read).
In this case, *if* the claims of Z-Ram stands up, it can be used as
the basis to construct caches that's tens of MB in size with better
power consumption characteristics, better SEU tolerance than SRAM,
smaller die area, all at a comparable access speed to an SRAM block
of equal capacity. If it's slightly faster, great. If it's slightly
slower, no big deal. L3 caches are about capacity rather than speed,
and +/- 20% in speed is not a big deal.
I note that SOITEC is an investor in