Ian said:
Yes, S3 shuts down more motherboard resources than S1,
but even for S3 the Northbridge remains active to supply
the memory refreshing, without which, the contents would
be lost. The PSU is still fully operational, although the
current draw is not as great. The 3.3V supply is still needed
to provide the 1.8V or 1.5V memory power for DDR2 or DDR3.
The +5VSB has nothing to do with preserving the RAM
contents. The sleep mode on current motherboards is S3,
which is what I was talking about. With S1, basically only
the CPU is halted, although it's the fastest to wake up,
because all you have to do cancel the Halt state and you're
going again.
Get your multimeter out and test that theory!
In S3, only the +5VSB is running.
When the main outputs on a power supply are running,
the fan runs. When the power supply main outputs are
off, there is a separate circuit that generates only
+5VSB. That is what is used to power the RAM in S3
suspend to RAM.
Here is a schematic for an ATX power supply. The
bottom left corner of the schematic, is the separate
circuit for +5VSB. It takes the rectified AC from the
wall, that has been filtered by the primary side
capacitor, and converts it to +5VSB. This supply
is actually using a linear, to create the final
output.
http://www.pavouk.org/hw/en_atxps.html
There is a schematic for a motherboard here. Flip
to PDF page 80. This is a switching regulator supplying
2.5V to DDR DIMMs. When the computer is running, the
MOSFETs Q6H1 and Q6H2 produce switching regulator
output, powerful enough to provide the few amps
needed by the DDR memory. Q6G1 is a backfeed cut,
to prevent current from flowing backwards.
http://www.intel.com/design/chipsets/schematics/252812.htm
The regulator is a Semtech SC2614. Flip to PDF page 6
for a block diagram of the regulator. 5VSTBY on the
left, goes to an internal "Stby LDO", which stands
for "Standby Low DropOut Linear Regulator". When the
computer goes to sleep, VDDQSTBY is the source
of 2.5V current, for the memory which is in self-refresh.
It looks like the PWRGD, presumably derived from
Power_Good on the motherboard, is used to control whether
the LDO is operational or not. Using a linear regulator
is only possible, if the current draw is pretty low, and it
should be for self-refresh. When VDDQSTBY is operating,
the gate drive should be removed from the switching
MOSFETs. Thus, the SC2614 switches from converting
regular rail voltage into 2.5V for the DIMMs, to using
+5VSB via the LDO path to make 2.5V.
http://www.semtech.com/pc/downloadDocument.do?id=468
HTH,
Paul
