toebens said:
Hi,
my computer has 6 usb ports on the back of the motherboard and has 2
ports on the front (8 ports all). The system is pretty new (chipset
Intel 965 Express if i remember well).
The Windows XP device manager shows up:
5x Intel ICH8 Family USB Universal Host Controller
2x Intel ICH8 Family USB2 Enhanced Host Controller
1x USB Mass Storage Device
7x USB Root Hub
I would like to know:
a) how many USB 2.0 devices can i connect to the computer that will
also work in usb 2.0 (in high speed 480mbit/s!) each??
only 2 (because of only 2 enhanced host controllers!?)?
is every port woking in 2.0 high speed or only 2 ports (2x usb 2.0; 5x
usb 1.x!?)?
b) will i only be able to connect 7 devices to it (without hub)? so i
will have one physical port unused?
c) is every usb 2.0 port woking in high speed each? or do they all
share the 480mbit/s?
d) if i connect a usb hub to a port on my motherboard will all devices
that are connected to the usb hub share the bandwidth?
I need the best possible performance because i plan to use a
professional usb 2.0 asio soundcard, 4x external PATA harddisks in
external usb 2.0 cases, keyboard, mouse and digicam.
Thank you, toebens
This is from the ICH8 datasheet. Developer.intel.com is the source of
such things...
*******
USB EHCI Host Controllers (D29:F7 and D26:F7)
The ICH8 contains two Enhanced Host Controller Interface (EHCI) host controllers
which support up to ten USB 2.0 high-speed root ports. USB 2.0 allows data transfers
up to 480 Mb/s using the same pins as the ten USB full-speed/low-speed ports. The
ICH8 contains port-routing logic that determines whether a USB port is controlled by
one of the UHCI controllers or by one of the EHCI controllers. USB 2.0 based Debug
Port is also implemented in the ICH8.
A summary of the key architectural differences between the USB UHCI host controllers
and the EHCI host controller are shown in Table 78.
Table 78. UHCI vs. EHCI
Parameter USBUHCI USBEHCI
Accessible by I/O space Memory Space
Memory Data Structure Single linked list Separated in to
Periodic and
Asynchronous lists
Differential Signaling Voltage 3.3V 400 mV
Ports per Controller 2 6 (controller #1) and
4 (Controller #2)
*******
To explain how this works, would require drawing an ugly diagram. So I'll try words instead.
The datasheet claims there are up to 10 ports. Sometimes a port or two is used for
some motherboard purpose. Or in some cases, there are so many USB ports, they just don't
provide headers for them all.
Say there are 10 ports. There are five USB 1.1 logic blocks inside the Southbridge.
Each USB 1.1 block, connects to a "stack" of two USB connectors. So for best
data transfer performance at the USB 1.1 level, use only one of the two USB
connectors in a stack. (Both 2x5 motherboard headers, and the USB connectors on the
back of the computer, are grouped as pairs of ports.)
As well as five USB 1.1 logic blocks, there are also USB2 logic blocks. The
connecting of these blocks is dynamic. A dynamic binding if you will.
If it is determined a device is USB2 capable, the USB I/O is disconnected logically
from the USB 1.1 logic block, and is connected to a USB2 logic block.
The excerpt from the datasheet above, claims there are two USB2 controllers. One
controller serves three stacks of two connectors each. If any of those I/O connections
require USB2 services, that particular USB2 controller is used.
A separate USB2 controller handles two stacks of two connectors each.
For absolute best performance, where I/O were overlapped by software (i.e. software
is not limiting you to synchronous I/O and only accessing one USB at a time), you'd
want to plug a USB2 device, into a port on the 6 connector pool. And a second device
on the 4 connector pool. You would have a total of 120MB/sec I/O bandwidth,
60MB/sec on each device.
The USB2 controller logic block, has a total of 60MB/sec of bandwidth. It is shared
over the pool of connectors it controls. If you had six identical devices, and
async software access, then each would get a 10MB/sec share. Looking at the four
connector pool, the 60MB/sec there, would result in 15MB/sec average being
available to the four connected devices. Note that the data rate on the cables,
is still 480 megabits/sec, but the duty cycle (how often packets can be on any
link) is limited by the available bandwidth of the USB2 logic block. As far as
I know, USB "polls" the endpoints, for work to do, so a USB2 controller would
be scanning the up to six bound ports, sequentially, looking for work to do.
The reason they are not split "5 + 5", is because of the "stack of two" relationship.
You wouldn't want a "stack of two", that uses the same USB 1.1 logic block, to span
the domain of two USB2 logic blocks. So in that sense, one USB2 block is paired with
three USB1.1 blocks, while the second USB2 block is paried with two USB1.1 blocks.
Probably clear as mud...
OK, I did find a figure in the datasheet. See PDF page 218, Figure 16.
http://download.intel.com/design/chipsets/datashts/31305603.pdf
And if that doc isn't big enough for you, the USB20 spec is here.
At 650 pages, designers use a paper copy of this, to keep their
office door open
http://www.usb.org/developers/docs/usb_20_071607.zip
HTH,
Paul
