I recollect seeing mention of PCI Express payload size in some
earlier BIOS screens. But doing a search right now, is indicating
what the hardware is doing, is something quite different.
This article, would have you believe that you just turn a knob,
and by magic, that is what you get. I got a similar impression
by reading BIOS manuals, that the hardware really could support
all those values.
http://www.techarp.com/showFreeBOG.aspx?lang=0&bogno=387
Now, if I look at some actual hardware company documentation,
the numbers quoted are quite different.
http://www.xilinx.com/support/answers/22880.htm
"Currently most if not all devices available on the market
support 256 byte MPS values or less"
http://www.plxtech.com/pdf/technical/expresslane/Choosing_PCIe_Packet_Payload_Size.pdf
"1.1 Market Segmentation of Maximum Payload Support
We observe distinct market segmentation in the support for
various maximum payload values. Intel desktop chipsets support
at most a 64-byte maximum payload while Intel server chipsets
support at most a 128-byte maximum payload. The primary reason
for this is to match the cache line size for snooping on the front
side bus. A secondary reason may be that the memory controller
itself is optimized around handling cache line sizes. Finally,
the buffer memory required is roughly proportional to the maximum
payload size; supporting longer packets raises device cost. The
majority of the market is well served with a maximum payload of
256 bytes or less.
Chipsets produced by vendors other than Intel have supported a
higher value; 512 bytes is the commonly known maximum payload
value for a server North Bridge. As will be shown later, this
value provides higher throughput for storage and network traffic
and in fact seems to mark the point of diminishing returns, except
for a specialized storage infrastructure.
The storage infrastructure is optimized to transfer long files
segmented into disk sector size payloads of 2K- or 4K-bytes.
Storage ASSPs typically support payloads of up to 4 K-bytes and
in most cases exhibit less than optimal performance with shorter
packet lengths due to internal architectural tradeoffs and lack
of large packet-size support in other components in the path of
transfer. This is the case for storage “boxes” as opposed to
storage HBAs that are limited by the North Bridge’s maximum
payload capability. Most storage OEMs have adopted to short
payload restrictions but a small percentage of systems using
proprietary North Bridge function through custom ASICs have been
consistent in requiring support for longer packet lengths."
The reason I decided to look that stuff up, is I was having
trouble finding a board to match your requirement. It isn't a
problem finding a bandwidth monster, in terms of lanes, but
the BIOS setting in question has largely disappeared from the
latest generation of BIOS. (PEG buffer size)
I'd probably try something with a 790i, as a way to get
some bandwidth. This one has wiring for (3) x16 and (1) x8,
which meets your (4) x4 requirement. But I don't know what
the answer is to your TLP requirement.
P5N64 WS Professional
http://www.asus.com/products.aspx?l1=3&l2=11&l3=653&l4=0&model=2182&modelmenu=1
http://c1.neweggimages.com/NeweggImage/productimage/13-131-321-04.jpg
