Seeking advices on generating a tracking pulse with nano-seconds precision

  • Thread starter Thread starter Johnson
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J

Johnson

Hi there,

I believe it is easy to use a high-end digital oscillator these days to
generate a tracking pulse with a few nanoseconds delay compared to the
reference pulse. However, I am thinking about the possibility to
implement the task in a different way, a lower-cost way.

Last month I designed a small circuit to generate the reference pulse
sequence at 35.42MHz with DW9255 (35.42M central freq plus max 300ns
GDR)at board. Now I want to add a few more components to the board so I
can generate a tracking pulse sequence as well. I want the tracking
pulse sequence is only a few nano-seconds delay compared to the
inputing pulse sequence, and I want the delay between them is as stable
as possible. For example, 10 nanoseconds delay with 1 nanosecond drms.
In other word, I only care about the time difference stability between
these two sequences.

I am thinking about any possibilties at this moment and their costs as
well, for example, a positive feedback circuit. Could anybody please
provide me some ideas to implement this task? Lower cost will be
better.

Thanks in advance.

Johnson
 
Johnson said:
Hi there,

I believe it is easy to use a high-end digital oscillator these days to
generate a tracking pulse with a few nanoseconds delay compared to the
reference pulse. However, I am thinking about the possibility to
implement the task in a different way, a lower-cost way.

Last month I designed a small circuit to generate the reference pulse
sequence at 35.42MHz with DW9255 (35.42M central freq plus max 300ns
GDR)at board. Now I want to add a few more components to the board so I
can generate a tracking pulse sequence as well. I want the tracking
pulse sequence is only a few nano-seconds delay compared to the
inputing pulse sequence, and I want the delay between them is as stable
as possible. For example, 10 nanoseconds delay with 1 nanosecond drms.
In other word, I only care about the time difference stability between
these two sequences.

I am thinking about any possibilties at this moment and their costs as
well, for example, a positive feedback circuit. Could anybody please
provide me some ideas to implement this task? Lower cost will be
better.

Thanks in advance.

Johnson
Click to expand...

In years past, there were some ECL logic level delay lines,
with programmable delay. A search term like "ecl programmable delay line"
might turn up a few. At least one of those products, was based on
gate delays, instead of using a network of LCs. Sometimes the
physical packaging of the device, gives away the implementation
method:

This one uses gate delays:
http://www.onsemi.com/pub/Collateral/MC10E196-D.PDF

This one is large enough to house LC networks and selector logic:
http://www.datadelay.com/datasheets/pdu1032h.pdf

There are some more modern programmable delay lines here. Intrinsic
delay 10ns plus delta delay (0..255)*0.15ns (DS1020-15 near the bottom).

http://para.maxim-ic.com/compare.asp?Fam=ProgDel&Tree=Timers&HP=Timers.cfm&ln=

Perhaps one of the newsgroups in "sci.electronics" would be a better
place to ask a more detailed question - you should include more
background details on what you are trying to do, because your biggest
advantage first, is deciding whether the architecture of what you are
building is correct. Implementation is only a small part of the answer.

Paul
 
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