If it's a P4 platform, where the FSB is quad-pumped (4 transfers per
clock cycle), the data throughput of the FSB is (approaching) double
that of the memory, assuming DDR memory. In that situation the memory
is the bottleneck. While you could keep both busses synchronous,
raising the FSB until the memory has reached it's ceiling speed, which
would be maximal performance, the problem with doing that is you'll
hit the ceiling frequency of the CPU, and the FSB can't be raised any
higher but the memory "might" not have reached it's ceiling yet.
If it's an Athlon platform, often there isn't any benefit to it.