Processor heat dissipation, Leakage current, voltages & clockspeed

[The little lost angel]

I know I'm a bit slow to start looking up this since the Prescott
thrust the issue into lime light. I didn't quite follow the major
discussion some weeks back. My friend got himself a spanking new
Prescott and claims it wasn't that hot despite claims. Yet Intel did
cancel the 4Ghz version so it got me thinking again whether the heat
increases dramatically with clockspeed. Since leakage was the big
thing thrown about, whether that was what increased with clockspeed.
And whether we could do any experiments to test it out.

So I started doing some reading up mainly from the tutorial document
posted some time back. Tried to understand these issues but don't
think I got very far. Would appreciate it greatly if the resident
experts here point out where I might have understood it wrongly.

I don't understand most of the explanations for how these are
calculated (most of the documents assume proficiency with mathematical
symbology which every regular visitor here knows by now I suck at
PPpP). So here's my best effort at arriving at something useful to
me as a layperson who's interested only in getting a useful real world
approximation of how these things are, say x.x rather than x.xxxxxx
kind of accuracy PpP

Reading, googling and all that, I get formulas and statement that
generally say that

Total Power = Dynamic Power + Static + Leakage + Short Circuit

Dynamic power is directly related to clockspeed. Leakage doesn't care
about clockspeed and is a function of the process/technology but
appears to be in direct relation with temperature, i.e. hotter
processors will leak even more power?.

I got a bit confused with a graph that displaying Leakage current vs
Vgs. http://www.cse.psu.edu/~vijay/iscatutorial/tutorial-sources.pdf
at pg 7. It seems to imply that lowering voltages will increase the
leakage??

Anyway, the point is, can I say that given the usual x86 processor.
The difference between the power dissipated at 3Ghz and at 4Ghz is
still mostly clockspeed.

Because dynamic power has to do with whether there's any actual
activity, both a 3Ghz and 4Ghz would have similar power draw when
idling since leakage will be there but dynamic would be very low.
While Static and Short are pretty much constant? Or would Short also
be directly related to the amount of activity since it's determined by
the slope of the signal so if there's no activity, there's no direct
current situation since there's no switching done.

So if we set the same (static becomes a constant) prescott at various
vcore (changes leakage right?), change the clockspeeds (changes
Dynamic), measure idle and load power dissipation, would we then be
able to calculate roughly the power used by Dynamic, Static, Short and
Leakage?

TiA!!!!

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[keith]

I know I'm a bit slow to start looking up this since the Prescott
thrust the issue into lime light. I didn't quite follow the major
discussion some weeks back. My friend got himself a spanking new
Prescott and claims it wasn't that hot despite claims. Yet Intel did
cancel the 4Ghz version so it got me thinking again whether the heat
increases dramatically with clockspeed. Since leakage was the big
thing thrown about, whether that was what increased with clockspeed.
And whether we could do any experiments to test it out.

So I started doing some reading up mainly from the tutorial document
posted some time back. Tried to understand these issues but don't
think I got very far. Would appreciate it greatly if the resident
experts here point out where I might have understood it wrongly.

You likely didn't. ;-)

I don't understand most of the explanations for how these are
calculated (most of the documents assume proficiency with mathematical
symbology which every regular visitor here knows by now I suck at
PPpP). So here's my best effort at arriving at something useful to
me as a layperson who's interested only in getting a useful real world
approximation of how these things are, say x.x rather than x.xxxxxx
kind of accuracy PpP

Reading, googling and all that, I get formulas and statement that
generally say that

Total Power = Dynamic Power + Static + Leakage + Short Circuit

You're author uses some pretty strange terminology, but it's really
somewhat simpler (and more complicated than that. Very little in a
processor these days is what a your author would call "static". The
PLL would have its static aspects, and likely nothing else. The term
"static power" is considered to be "leakage".

"Short circuit" current, I've always heard called "shoot-through" and
lumped in with dynamic power, so your equation drops to two terms;
Dynamic and Static. ...not that these other things don't exist, they just
aren't that interesting to anyone other than the circuit designer.

Dynamic power is directly related to clockspeed.

And the square of the voltage. Note that the voltage may have to be
cranked up to get more GHz.

Leakage doesn't care
about clockspeed and is a function of the process/technology but appears
to be in direct relation with temperature, i.e. hotter processors will
leak even more power?.

Sure, and don't forget voltage. Leakage curent rises with something like
the square of the voltage (maybe even more), so static power rises by the
third power.

I got a bit confused with a graph that displaying Leakage current vs
Vgs. http://www.cse.psu.edu/~vijay/iscatutorial/tutorial-sources.pdf at
pg 7. It seems to imply that lowering voltages will increase the
leakage??

What they're pointing out is that when one reduces the design-point
Vdd, one must compensate by reducing the threshold voltage of the devices
(Vt must be less than Vdd or the gate won't switch). Lower Vt devices have
a sub-threshold leakage far worse than higher Vt devices. A particular
device doesn't leak more at lower voltages, rather it's a side-effect of
the choice (need) to go to a lower Vt device.

Anyway, the point is, can I say that given the usual x86 processor. The
difference between the power dissipated at 3Ghz and at 4Ghz is still
mostly clockspeed.

No, one makes certain design/processing choices to enable 4GHz. These
choices lead to higher power dissipation. If you took your 4GHz device
and ran it at 3GHz, and at the same voltage, then the dynamic power
difference would be simply the "clock speed" (i.e. 3/4 dynamic power), but
still the full static/leakage power. You wouldn't have reduced the total
power by 3/4. Of course you don't need the full Vdd at reduced frequency,
so you may be able to reduce that, which will lower the dynamic power
further (by the square of Vdd1/Vdd2) and static power (by perhaps the
cube).

Because dynamic power has to do with whether there's any actual
activity, both a 3Ghz and 4Ghz would have similar power draw when idling
since leakage will be there but dynamic would be very low.

Exactly. If you want to measure leakage power, shut the processor clocks
off (put the processor to sleep).

While Static and Short are pretty much constant? Or would Short also be directly
related to the amount of activity since it's determined by the slope of
the signal so if there's no activity, there's no direct current
situation since there's no switching done.

Yes, what you're calling "short" is "shoot-through" and can be considered
a component of the dynamic power. Though it's not directly related to any
capacitance, it walks like a duck.

So if we set the same (static becomes a constant) prescott at various
vcore (changes leakage right?), change the clockspeeds (changes
Dynamic), measure idle and load power dissipation, would we then be able
to calculate roughly the power used by Dynamic, Static, Short and
Leakage?

If you vary clock speed only, the Y-intercept (clock = 0) point would
indicate the leakage. At least at this level, forget "short" and
"static" power terms and include "static" and "leakage" in the static
term, and "dynamic" and "short" in the dynamic term:

Total = dynamic + static

 

[Johannes H Andersen]

I know I'm a bit slow to start looking up this since the Prescott
thrust the issue into lime light. I didn't quite follow the major
discussion some weeks back. My friend got himself a spanking new
Prescott and claims it wasn't that hot despite claims. Yet Intel did
cancel the 4Ghz version so it got me thinking again whether the heat
increases dramatically with clockspeed. Since leakage was the big
thing thrown about, whether that was what increased with clockspeed.
And whether we could do any experiments to test it out.

A CPU transistor is like an imperfect switch. If the switch is on or off,
no power is dissipated in the switch, but during the switching it
consumes most power when it's halfway between on and off. Hence for the
same device, the power consumption from switching is proportional to the
number of switchings in the circuit. The power can be reduced if the
switching itself can be made faster and/or the voltage/amp can be reduced.

 

[keith]

A CPU transistor is like an imperfect switch. If the switch is on or off,
no power is dissipated in the switch, but during the switching it
consumes most power when it's halfway between on and off. Hence for the
same device, the power consumption from switching is proportional to the
number of switchings in the circuit. The power can be reduced if the
switching itself can be made faster and/or the voltage/amp can be reduced.

That was more or less true five years ago, but as L'Angel is trying to
understand, this is no longer true. Deep sub-micron processes leak like
hell. ...so much so that the active power isn't the major worry going
forward.

BTW, even in your model, it's not the switch that dictates the power, but
the load (in this case capacitance).

 

[Johannes H Andersen]

That was more or less true five years ago, but as L'Angel is trying to
understand, this is no longer true. Deep sub-micron processes leak like
hell. ...so much so that the active power isn't the major worry going
forward.

BTW, even in your model, it's not the switch that dictates the power, but
the load (in this case capacitance).

Obviously, my model was simplified. A transistor is not a perfect switch,
hence it consumes power whether on or off, but maximum transistor power
is consumed during the switching halfway between on and off. The faster
it can switch, the less power is consumed. Smaller distances makes for
faster switching, but also apparently for higher leak currents, unless
some new structure or material can be found to keep the leaking under
control.

The increase in speed has always been dramatic and because the trend
has lasted 25 years, we expect it to continue as a matter of course. Ten
years ago or so I was thrown into studying parallel computing; it was
said that the trend in speed surely couldn't continue. Now this field
has matured and there many really nice parallel algorithms, but the
problem it that it's a niche field; the systems were/are expensive and
manufacturer specific, not really suitable for standard software products.
I often spent more time 'parallizing' than on the problem I wished to
solve. Moreover, the resulting programs became 'solidified' and virtually un-maintainable.
Nevertheless, I learned many small habits which might
help in a pipelined environment, such as e.g. unrolling and looping
matrix multiplications the best way round.

 

[keith]

Obviously, my model was simplified.

....to the point of being useless. What you said was more or less true
five years ago. It is *not* today.

A transistor is not a perfect switch,
hence it consumes power whether on or off, but maximum transistor power
is consumed during the switching halfway between on and off.

That is not true. You're only considering what L'Angel's reference
called, "short circuuit" power. By no means is this a huge deal, nor has
it ever been, with the exception of some really exotic high-power logic
(like 74ASxxx and 74Fxxx).

The faster it can switch, the less power is consumed.

Wrong. The capacitance on the load is the same, so the same charge is
transfered, thus the same power dissipated. ...all else equal.

Smaller distances makes for faster switching,

Irrelevant. All else being the same, the same charge is transfered. This
is why (for a goven processor) the active power dissipation is
proportional to the frequency.

but also apparently for higher leak currents, unless
some new structure or material can be found to keep the leaking under
control.

Deep sub-micron processes leak like sieves, yes, but that's a different
issue than what you raise above.

The increase in speed has always been dramatic and because the trend has
lasted 25 years, we expect it to continue as a matter of course.

"We"?? LOL Face the facts. *We* are fetting periously close to atomic
dimensions and the voltage gadients are constantly flirting with the MV/cm
"limit". *Wee* now have 100A on a chip, not much bigger across than the
wire supplying power to your eletric stove. ...and the current is alll on
the "surface". The power density of these things are on the order of a
*BILLION* times that of ol' Sol. Another 25 years? I'm glad I'm not
going to be the one whipped into producing that fantasy. ;-)

Ten years ago or so I was thrown into studying parallel computing; it was
said that the trend in speed surely couldn't continue. Now this field
has matured and there many really nice parallel algorithms, but the
problem it that it's a niche field; the systems were/are expensive and
manufacturer specific, not really suitable for standard software
products. I often spent more time 'parallizing' than on the problem I
wished to solve. Moreover, the resulting programs became 'solidified'
and virtually un-maintainable. Nevertheless, I learned many small habits
which might help in a pipelined environment, such as e.g. unrolling and
looping matrix multiplications the best way round.

??? Where did this change-of-subject come from?

 

[The little lost angel]

And the square of the voltage. Note that the voltage may have to be
cranked up to get more GHz.

Sure, and don't forget voltage. Leakage curent rises with something like
the square of the voltage (maybe even more), so static power rises by the
third power.

So both the dynamic power and static power rises exponentially to the
voltage applied? Thus if I take a 3Ghz Prescott, changes the voltage
from say 1.4V to 1.5V and measure an increase of 5W power while idle,
this would imply that the increase in leakage current is 500A!?? Since
the current increases with the square, so 5W = 0.1*0.1 * A therefore 5
/ 0.01 = A = 500A? At cube, it becomes even crazier

Ok, I did that before I saw the formula you gave later as (VDD1/VDD2),
thus is it (1.4/1.5)^3 * A = 5, hence A= 6.15 which sounds a WHOLE lot
more credible. Would this also mean that the actual leakage can be
1.5V x 6.15A = 9W or would it be 1.5V x (6.15A + X) where X was the
original leakage current at 1.4V?

Please don't laugh too hard if the maths is hopelessly naive & wrong
PPPP

What they're pointing out is that when one reduces the design-point
Vdd, one must compensate by reducing the threshold voltage of the devices
(Vt must be less than Vdd or the gate won't switch). Lower Vt devices have
a sub-threshold leakage far worse than higher Vt devices. A particular
device doesn't leak more at lower voltages, rather it's a side-effect of
the choice (need) to go to a lower Vt device.

Hmm, I'm getting a little confused (as usual). Maybe it's because I
don't truly understand what's Vdd and Vt. Am I correct to understand
that Vdd is what's commonly known as VCore, i.e 1.4V for the Prescott,
while Vtt is some internal design parameter that we will not know, e.g
1.3V for the Prescott. Therefore if they attempted to drop the VCore
to say 1.2V and therefore drop the internal Vt to say 1.1V to
compensate, the leakage problem will increase even though the voltages
had dropped?

How would this play out with the decrease in leakage current since
voltage dropped and leakage responds exponentially to that? Can it be
said that theoretically it can be designed so that the decrease in
leakage from the voltage drop cancels out the increase in sub
threshold leakage so that using a lower Vdd/Vt won't hurt in terms of
leakage current and therefore help lower the total power dissipation
since dynamic power will be drastically reduced with lower VCore/Vdd?

Would this Vt/Vdd issue be also the reason for the popular practise of
raising VCore to get higher clockspeeds for the overclockers. Since
it's been mentioned higher voltages help transistors switch faster.
i.e. the transistors cannot switch faster at the default Vt say 1V and
in order to do say 4Ghz, it needs to up Vt to say 1.35V and at the
default VCore of 1.4V, the difference isn't big enough to allow this.
Hnece raising VCore to 1.5V then allows the overclocker to overcome
the designed Vdd/Vt limits?

Exactly. If you want to measure leakage power, shut the processor clocks
off (put the processor to sleep).

Is this the same as the normal idling mode or would it be a special
function that can be enabled by software i.e. sending a particular
instruction to the processor and see the PC stop responding? Or would
we get a good approximation by compiling a small asm program running
in DOS (or maybe some bare minimum linux kernel to minimize OS
interference) that does nothing except endless loop of HLT? Since
googling about this imply that HLT only puts the processor to sleep
until the next interrupt. This would be relatively often due to the
real time clock interrupt isn't it?

If you vary clock speed only, the Y-intercept (clock = 0) point would
indicate the leakage. At least at this level, forget "short" and
"static" power terms and include "static" and "leakage" in the static
term, and "dynamic" and "short" in the dynamic term:
Total = dynamic + static

Thanks for making it simpler & clearer!!! *hugz*

Now to figure out a way to make it clock=>0 so that I can sate my
curiousity pPpP

--
L.Angel: I'm looking for web design work.
If you need basic to med complexity webpages at affordable rates, email me
Standard HTML, SHTML, MySQL + PHP or ASP, Javascript.
If you really want, FrontPage & DreamWeaver too.
But keep in mind you pay extra bandwidth for their bloated code

 

[Keith R. Williams]

So both the dynamic power and static power rises exponentially to the
voltage applied? Thus if I take a 3Ghz Prescott, changes the voltage
from say 1.4V to 1.5V and measure an increase of 5W power while idle,
this would imply that the increase in leakage current is 500A!?? Since
the current increases with the square, so 5W = 0.1*0.1 * A therefore 5
/ 0.01 = A = 500A? At cube, it becomes even crazier

I don't follow your numbers at all. The change from 1.4V to 1.5V is 7%
(1.4V * 1.07 = 1.5), so the dynamic power will change by the square of
7% (1.07 * 1.07) or about 15%. The static power (assume a cube) would
change by about 22% (1.07 * 1.07 * 1.07).

Ok, I did that before I saw the formula you gave later as (VDD1/VDD2),
thus is it (1.4/1.5)^3 * A = 5, hence A= 6.15 which sounds a WHOLE lot
more credible. Would this also mean that the actual leakage can be
1.5V x 6.15A = 9W or would it be 1.5V x (6.15A + X) where X was the
original leakage current at 1.4V?

I still don't follow your variables (what's 'A'?), though yes, the
dynamic power is proportional to the frequency and voltage squared, so
you can't take the absolute voltage, rather the change in voltage.

Please don't laugh too hard if the maths is hopelessly naive & wrong
PPPP

Hmm, I'm getting a little confused (as usual). Maybe it's because I
don't truly understand what's Vdd and Vt. Am I correct to understand
that Vdd is what's commonly known as VCore, i.e 1.4V for the Prescott,
Yes.

while Vtt is some internal design parameter that we will not know, e.g
1.3V for the Prescott. Therefore if they attempted to drop the VCore
to say 1.2V and therefore drop the internal Vt to say 1.1V to
compensate, the leakage problem will increase even though the voltages
had dropped?

Your numbers are way off for Vt, but essentially yes. Vt is the
voltage that must be applied between the gate and source for the
transistor to turn "on". This is a device design parameter. Obviously
if this "threshold" (line between "on" and "off") voltage is higher
than the core voltage, the device is rather useless (can never be
turned on).

How would this play out with the decrease in leakage current since
voltage dropped and leakage responds exponentially to that? Can it be
said that theoretically it can be designed so that the decrease in
leakage from the voltage drop cancels out the increase in sub
threshold leakage so that using a lower Vdd/Vt won't hurt in terms of
leakage current and therefore help lower the total power dissipation
since dynamic power will be drastically reduced with lower VCore/Vdd?

One can play all sorts of games balancing power, however the device
still has to function and be marketable. Lowering Vt tends to make the
devices faster, though more leaky. One can drop the Vcore (Vdd, where
'd' = drain) to compensate, but the circuit gets slower again. There
are all sorts of knobs to twist and many counteract others. The trick
is to find the right mix of knob settings.

Would this Vt/Vdd issue be also the reason for the popular practise of
raising VCore to get higher clockspeeds for the overclockers. Since
it's been mentioned higher voltages help transistors switch faster.

It's not so much that Vt is important here, but yes a higher Vcore
raises the current so capacitors charge faster. It also raises the
power => temperature.

i.e. the transistors cannot switch faster at the default Vt say 1V and
in order to do say 4Ghz, it needs to up Vt to say 1.35V and at the
default VCore of 1.4V, the difference isn't big enough to allow this.
Hnece raising VCore to 1.5V then allows the overclocker to overcome
the designed Vdd/Vt limits?

Vt is a design parameter and really doesn't have all that much to do
with over-clocking. It's locked into the design by the device physics;
raising Vdd doesn't change Vt. It does make circuits faster because of
the higher charging current.

Is this the same as the normal idling mode or would it be a special
function that can be enabled by software i.e. sending a particular
instruction to the processor and see the PC stop responding? Or would
we get a good approximation by compiling a small asm program running
in DOS (or maybe some bare minimum linux kernel to minimize OS
interference) that does nothing except endless loop of HLT? Since
googling about this imply that HLT only puts the processor to sleep
until the next interrupt. This would be relatively often due to the
real time clock interrupt isn't it?

Either will approximate this. However there are still clocks going to
the caches and bus logic (for cache snoops) in these modes. Some deep-
sleep modes (perhaps hybernation or suspend-to-disk) may shut down the
clocks. You'd have to consult the specs of the processor/system to be
sure.

Thanks for making it simpler & clearer!!! *hugz*

Now to figure out a way to make it clock=>0 so that I can sate my
curiousity pPpP

Curious... How are you going to measure the device power/current?

 

[Franc Zabkar]

So both the dynamic power and static power rises exponentially to the
voltage applied? Thus if I take a 3Ghz Prescott, changes the voltage
from say 1.4V to 1.5V and measure an increase of 5W power while idle,
this would imply that the increase in leakage current is 500A!?? Since
the current increases with the square, so 5W = 0.1*0.1 * A therefore 5
/ 0.01 = A = 500A? At cube, it becomes even crazier

Ok, I did that before I saw the formula you gave later as (VDD1/VDD2),
thus is it (1.4/1.5)^3 * A = 5, ...

VDD1/VDD2 is a dimensionless quantity. Hence the units on both sides
of your equation do not balance, ie on the left you have amps, while
on the right you have watts. Then there's your mistake in equating
ratiometric changes with absolute ones ...

... hence A= 6.15 which sounds a WHOLE lot
more credible. Would this also mean that the actual leakage can be
1.5V x 6.15A = 9W or would it be 1.5V x (6.15A + X) where X was the
original leakage current at 1.4V?

Please don't laugh too hard if the maths is hopelessly naive & wrong
PPPP

- Franc Zabkar

 

[Franc Zabkar]

Curious... How are you going to measure the device power/current?

I suppose you could get a rough idea by monitoring the power
consumption on the AC side with a wattmeter. Of course this figure
would be influenced by the PSU's efficiency, but you could estimate
this by testing with a fixed resistive load on the +5V rail, say. For
example, if adding a 20W DC load drew an additional 25W from the
mains, then the PSU's efficiency would be 80%.


- Franc Zabkar

 

[Johannes H Andersen]

...to the point of being useless. What you said was more or less true
five years ago. It is *not* today.


That is not true. You're only considering what L'Angel's reference
called, "short circuuit" power. By no means is this a huge deal, nor has
it ever been, with the exception of some really exotic high-power logic
(like 74ASxxx and 74Fxxx).


Wrong. The capacitance on the load is the same, so the same charge is
transfered, thus the same power dissipated. ...all else equal.


Irrelevant. All else being the same, the same charge is transfered. This
is why (for a goven processor) the active power dissipation is
proportional to the frequency.


Deep sub-micron processes leak like sieves, yes, but that's a different
issue than what you raise above.


"We"?? LOL Face the facts. *We* are fetting periously close to atomic
dimensions and the voltage gadients are constantly flirting with the MV/cm
"limit". *Wee* now have 100A on a chip, not much bigger across than the
wire supplying power to your eletric stove. ...and the current is alll on
the "surface". The power density of these things are on the order of a
*BILLION* times that of ol' Sol. Another 25 years? I'm glad I'm not
going to be the one whipped into producing that fantasy. ;-)


??? Where did this change-of-subject come from?

That I haven't answered is no indication that I agree with you. It just
means that I've given up.

 

[keith]

I suppose you could get a rough idea by monitoring the power
consumption on the AC side with a wattmeter. Of course this figure
would be influenced by the PSU's efficiency, but you could estimate
this by testing with a fixed resistive load on the +5V rail, say. For
example, if adding a 20W DC load drew an additional 25W from the
mains, then the PSU's efficiency would be 80%.

Forget the efficiency (which is not a constant). How do you shut down the
clocks to the CPU without "suspending" the rest of the system? Theidea
here is to measure the CPU, or more precisely the technology, not the
entire system. To do that the processor power has to be isolated. While
this certainly can be done, it's not something a casual user could do.

 

[keith]

That I haven't answered is no indication that I agree with you. It just
means that I've given up.

Ah, so I get the last word?

 

[The little lost angel]

Forget the efficiency (which is not a constant). How do you shut down the
clocks to the CPU without "suspending" the rest of the system? Theidea
here is to measure the CPU, or more precisely the technology, not the
entire system. To do that the processor power has to be isolated. While
this certainly can be done, it's not something a casual user could do.

Hmm, my new (relatively) ISP screws up my newsfeed again as usual. I
don't see where Keith asked the original question.

But well, you know my age old project that never took off the ground
due to the various constraints. So part of that included a bridge bit
where we could plug in a PSU and split out the different rails for
measuring current. So what we thought we could do was to use it and
measure the +12V going to the processor since as far as I'm aware (my
fault if wrong, since I do most of the internet research), they are
supposed to feed the P4 from the +12V only.

The last time we tried it, when processor load goes up, the +5V
current doesn't move. The 3.3V and +12V moved. But since the 3.3V
supplies the RAM, it would make sense that when processing stuff, the
3.3V draw will increase.

So we would have isolate the +12V mostly. I got the Infineon spec pdf
for the power mosfet (hey I knew all that hanging around in S.E.B. was
going to come in handy!) on his motherboard. So we can account for
losses due to the conversion inefficiency.

Then we planned to swap the graphic cards, # of RAM modules, as well
as run the system without a processor to determine as far as we can,
what's being used by the rest of the system.

On top of that I figured that the system power draw should be
relatively constant, so S + CPU_Dyn + CPU_Leak = X. Since we can
control the VCore, the ClockSpeed, I thought we might be able to do
enough variations to calculate the different parts somehow.

Like I said, it's just for sating curiousity so I think it's good
enough accuracy. I'm not trying to engineer a processor or motherboard
or something! pPpP

--
L.Angel: I'm looking for web design work.
If you need basic to med complexity webpages at affordable rates, email me
Standard HTML, SHTML, MySQL + PHP or ASP, Javascript.
If you really want, FrontPage & DreamWeaver too.
But keep in mind you pay extra bandwidth for their bloated code

 

[Franc Zabkar]

Reading, googling and all that, I get formulas and statement that
generally say that

Total Power = Dynamic Power + Static + Leakage + Short Circuit

I don't claim to have any significant knowledge in this area, but the
tutorial document you refer to
(http://www.cse.psu.edu/~vijay/iscatutorial/tutorial-sources.pdf) does
not mention static power.

Instead it states that...

Total Power = Dynamic Power + Short Circuit + Leakage

P = C x Vdd^2 x P0->1 x f
+ tsc x Vdd x Ipeak x P0->1 x f
+ Vdd x Ileakage

AFAICS, the term P0->1 represents signal activity and is the
probability that a gate will change state. No signal activity would
mean that P0->1 = 0 and hence dynamic and SC power would be zero.

I've done some reading myself and collected a whole bunch of
references which generally state that static power and leakage power
are the same thing. Only one distinguishes between the two, but the
explanation is a bit sparse. So I confess I'm confused on this point.

Here are some of the online documents I managed to find:

http://www.elecdesign.com/Articles/ArticleID/8494/8494.html

"An intellectual-property (IP) platform reduces dynamic and static
(leakage) power in mobile chips built on generic 130-nm process
technologies."

http://www.ece.utexas.edu/~adnan/vlsi-04/lec18LowPower.ppt

Static power = leakage power

http://www.imm.dtu.dk/~s973591/

"The continuous miniaturization of VLSI-circuits is driven by a demand
for higher circuit speeds and lower power consumption. But as a result
of the lower supply voltages sub-threshold leakage currents become
significant. Transistors are no longer completely turned off but leak
continuously and static power consumption is therefore no longer
negligible in 90 nm and smaller processes. Leakage power has been
reported to be as much as 50% of total power consumption in actual
chips produced."

http://csdl.computer.org/comp/mags/co/2003/12/rz068abs.htm

"Off-state leakage is static power, current that leaks through
transistors even when they are turned off."

http://www.imm.dtu.dk/~stassen/Projects/IMM/lpdesign.htm

"Static power consumption ... is caused by leakage currents while the
circuit is idle, i.e. not performing computations."

http://www.ohiolink.edu/etd/view.cgi?ucin982010436

"The leakage current, which leads to static power is becoming an
increasingly important part of the power dissipation."

http://arstechnica.com/articles/paedia/cpu/prescott.ars/2

"To sum up the quote above, the amount of power dissipation due to
leakage current is 44% higher in the P-III 1.13 GHz than in the P-III
1.0 GHz. In other words, taking the same chip and upping the clock
speed also significantly increase the total leakage current flowing
through the chip.

The overall problem is that leakage current has been increasing at a
much faster rate than dynamic current, or the current that flows
through the transistors when they're in the "on" position. If this
trend continues, it will lead to a situation where the leakage current
begins to approach the dynamic current;"

http://www.citris-uc.org/projmatrix/project/display.action?project.id=63

"In nanometer scale CMOS technologies, static power consumption will
be the major component of the overall power consumption. Static power
has been rapidly growing as technologies have scaled supply voltage
VDD and threshold voltage Vth down to maintain drive current and
reduce dynamic power consumption, at the cost of an exponential
increase in transistor leakage currents. Static power can be as much
as 20% of the power budget of current highend microprocessors, and
this will likely increase as future technologies continue to reduce
Vth."

http://www.lowpower.de/charter/designguide_2.php

This chapter gives an overview of the sources of power consumption. A
formula for average power is given in equation 1.

equation 1: Pavg = Pdynamic + Pshort + Pleakage + Pstatic

V^3 dependency for dynamic power:
http://www.intel.com/technology/itj/2003/volume07issue02/art03_pentiumm/p03_awareness.htm
http://books.nap.edu/html/embedded_everywhere/ch2_b3.html


- Franc Zabkar

 

[Franc Zabkar]

I don't follow your numbers at all. The change from 1.4V to 1.5V is 7%
(1.4V * 1.07 = 1.5), so the dynamic power will change by the square of
7% (1.07 * 1.07) or about 15%. The static power (assume a cube) would
change by about 22% (1.07 * 1.07 * 1.07).

All but one of the online references I have found state that static
power = leakage power. None talk about a cubic dependency on Vdd. The
only cubic dependency is for dynamic power (see my other post in this
thread). It's all very confusing ...


- Franc Zabkar

 

[Franc Zabkar]

Forget the efficiency (which is not a constant).

That may be true if the PSU is operating at low power, but the
efficiency would be fairly constant if the PSU were operating near its
rated load. In any case, one could measure the AC power draw at DC
increments of 5W, 10W, 15W, and 20W, say, and then extrapolate one's
results to 0W. This non-linear (?) calibration curve could then be
used to accurately estimate the increased DC load (of the entire
system) resulting from changes in frequency or Vcore, for example. In
fact one could go the whole hog and measure the PSU's AC power
consumption at DC loads from 0W to 400W, say.

How do you shut down the
clocks to the CPU without "suspending" the rest of the system? Theidea
here is to measure the CPU, or more precisely the technology, not the
entire system. To do that the processor power has to be isolated. While
this certainly can be done, it's not something a casual user could do.

That's why I said "you could get a rough idea". My intention was
merely to suggest a non-intrusive method that a "casual user could
do". The assumption (right or wrong) was that the CPU would be
responsible for the majority of the increase in power consumption.
IMO, the most accurate method would involve measuring the voltage
across the current sensing element(s) in the Vcore regulator. Some
regulators appear to use resistive links, while others use the RDSon
resistance of a MOSFET. The latter may be hard to quantify.


- Franc Zabkar

 

[keith]

All but one of the online references I have found state that static
power = leakage power. None talk about a cubic dependency on Vdd.

Leakage current, particularly gate tunneling, goes up by at *least* the
square of the voltage, this power goes as the cube. Sub-threshold current
is a similar issue. Think about the power dissipated in a diode, as it's
forward bias increase. Leakage is worse.

The only cubic dependency is for dynamic power (see my other post in this
thread).

Nope. Dynamic power goes with the square of the voltage. Think of a
CMOS switch as a charge pump. The charge goes up linearly with the
voltage, thus the power as the square.

It's all very confusing ...

Apparently. This is new territory for many.

 

[alexi]

I don't claim to have any significant knowledge in this area, but the
tutorial document you refer to
(http://www.cse.psu.edu/~vijay/iscatutorial/tutorial-sources.pdf) does
not mention static power.

Instead it states that...

Total Power = Dynamic Power + Short Circuit + Leakage

P = C x Vdd^2 x P0->1 x f
+ tsc x Vdd x Ipeak x P0->1 x f
+ Vdd x Ileakage

AFAICS, the term P0->1 represents signal activity and is the
probability that a gate will change state. No signal activity would
mean that P0->1 = 0 and hence dynamic and SC power would be zero.

I've done some reading myself and collected a whole bunch of
references which generally state that static power and leakage power
are the same thing. Only one distinguishes between the two, but the
explanation is a bit sparse. So I confess I'm confused on this point.

Actually, the VJ's article does mention "static" power, on Page1,
slide 2. For the overall power, the "leakage" and "static" can
be considered as same since they both are frequency-independent.
The difference between them is that the leakage is a parasitic
by accident (or by nature of transistor shrinking if you prefer),
while the "static" power is by circuit design. One example is
pseudo-nMOS circuits designed to speed up gates, see e.g.

http://www.ece.utexas.edu/~adnan/vlsi-04/lec9CctFamilies.ppt

The main page has some other important information on the topic,
e.g. Slide 12 of
http://www.ece.utexas.edu/~adnan/vlsi-04/lec18LowPower.ppt

If you check the above page, you will find again that for
most practical purposes the leakage current is considered
by modern engineering as being Vdd-independent. Therefore
the CPU quiescent power (leakage + static) is linear with
Vdd. The quadratic, cubic, or exponential dependency is
a product of imagination of Mr. Keith. He confuses Vdd with
temperature, where the dependence is substantial. Because
of the temperature effect (and finite junction-to-case
resistance), an indirect increase in measured quiescent
current can sometimes be confused with the effect of Vdd.

Regards,
-aap

 

[Franc Zabkar]

Leakage current, particularly gate tunneling, goes up by at *least* the
square of the voltage, this power goes as the cube. Sub-threshold current
is a similar issue. Think about the power dissipated in a diode, as it's
forward bias increase. Leakage is worse.

The tutorial that was alluded to by the OP distinguishes between
static power and leakage power. All other references appear to equate
the two concepts, as you have done. I would think that in the "static"
state as many as half the transistors could be ON and therefore
drawing significant current. The rest would be OFF and drawing a
comparatively negligible leakage current????

Nope. Dynamic power goes with the square of the voltage.

OK, so my statement was somewhat ambiguous. I meant that I found only
two online references that mentioned cubic dependency in relation to
power dissipation, and neither of these references talked about static
power or leakage, only dynamic power.

This is the first one:
http://www.intel.com/technology/itj/2003/volume07issue02/art03_pentiumm/p03_awareness.htm

The article discusses the Pentium M processor. It arrives at a cubic
dependency by assuming that frequency is proportional to Vcore. I
confess I don't understand the basis for this assumption.

This is the second article:
http://books.nap.edu/html/embedded_everywhere/ch2_b3.html

It examines the effects on power dissipation in an existing design
when it is scaled to a new technology. A cubic dependency arises
because newer processes result in lower capacitances and a lower
Vcore.

Think of a
CMOS switch as a charge pump. The charge goes up linearly with the
voltage, thus the power as the square.

Apparently. This is new territory for many.

Well, I understand the concept of leakage from my Uni days, and I
understand how the formula for dynamic power is derived. In the latter
case the energy stored by a capacitor is 1/2 * C * V^2, and this
energy is moved twice during one clock cycle. So power = (1/2 * C *
V^2) * 2f = C * V^2 * f.

That only leaves the concept of static power as opposed to leakage
power. I don't understand why some references distinguish between the
two, and others do not. How do these parameters differ, ie what are
the mechanisms underlying static power as opposed to leakage?


- Franc Zabkar