PCI Burst transfers initiated by the Northbridge

  • Thread starter Thread starter Bernhard Walle
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Bernhard Walle

Hello,

I want to know how PCI Burst transfers can be initiated by the CPU,
i.e. when does the host bridge start PCI burst transfers as initator?
I'm writing a device driver for Linux and I'm intersted about this
topic.

Can somebody point me to information about this topic or explain
the issue a bit? Thanks for any hints.


Regards,
Bernhard
 
If a PCI device has registers base+0, 4, 8, 0x10, and you write to them in
quick sequence, PCI bridge might combine the write to a burst.
 
Hello,

I want to know how PCI Burst transfers can be initiated by the CPU,
Click to expand...

By generating a request to an I/O device? ;-)
i.e. when does the host bridge start PCI burst transfers as initator?
I'm writing a device driver for Linux and I'm intersted about this
topic.

Can somebody point me to information about this topic or explain
the issue a bit? Thanks for any hints.
Click to expand...

It depends on the bridge. A classic Pentium cannot initiate a PCI
burst transfer. I/O devices easily can though.
 
By generating a request to an I/O device? ;-)


It depends on the bridge. A classic Pentium cannot initiate a PCI
burst transfer. I/O devices easily can though.
Click to expand...

It's a trick question.

Why in Big Hairy Thunderer's Name would one want a North Bridge to initiate
PCI burst transfers? Particularly for IO device service?

/daytripper
 
daytripper said:
It's a trick question.

Why in Big Hairy Thunderer's Name would one want a North Bridge to initiate
PCI burst transfers? Particularly for IO device service?
Click to expand...

Because of performance reasons? - The northbridge will combine writes
from the CPU to consecutive adresses in the PCI address space. By
definition, a write to memory, that is sent to the PCI bus, will be a
Memory Space access. IO Space accesses will only be initiated, when
the CPU does an IN or OUT instruction. The north bridge must not try
to combined the individual OUT's into a burst (cf the PCI spec).


Cheers,

Kai
 
Because of performance reasons? - The northbridge will combine writes
from the CPU to consecutive adresses in the PCI address space. By
definition, a write to memory, that is sent to the PCI bus, will be a
Memory Space access. IO Space accesses will only be initiated, when
the CPU does an IN or OUT instruction. The north bridge must not try
to combined the individual OUT's into a burst (cf the PCI spec).


Cheers,

Kai
Click to expand...

It is precisely about "performance reasons" that dictates why CPUs don't
initiate *write* bursts across PCI buses.

And you totally mistook "IO device service" as being synonymous with "IO
Space" accesses.

Bootstrap: you clearly have to go back to architectural basics and understand
why it is the *PCI agents* that inspire burst data transactions - in BOTH
directions - across the bus, not the North Bridge...

Cheers

/daytripper
 
A company I user to work for, had a PCI communication ASIC designed. For
some reasons, the PCI interface was not done right and would lock up if a
memory write burst was initiated by CPU bridge. And we took pains to make
sure we NEVER write to successive registers, otherwise burst occured and the
system was screwed.
 
A company I user to work for, had a PCI communication ASIC designed. For
some reasons, the PCI interface was not done right and would lock up if a
memory write burst was initiated by CPU bridge. And we took pains to make
sure we NEVER write to successive registers, otherwise burst occured and the
system was screwed.
Click to expand...

Shades of the early days of PCI, when erratum flew like confetti, and bios and
driver writers held chip designers hostage...

And yet another good reason not to use host-initiated bus transactions of any
stripe: Writes to memory mapped PCI space are *allowed* to be coalesced by the
host bridge. If the ASIC designers fail to implement their target state
machine to handle the resulting "burst" of register writes correctly to begin
with, the driver must utilize barrier instructions to get the write buffer
flushed between "register" writes, a pitiful way to run an airline...

/daytripper
 
daytripper said:
It is precisely about "performance reasons" that dictates why CPUs don't
initiate *write* bursts across PCI buses.
Click to expand...

There are actually PCI chips out there, that don't implement a DMA
engine. For those, you need to use the CPU (aka Programmed IO) to get
the data to the PCI chip. But we both know that. So what was the
point you were trying to make in the first place?
And you totally mistook "IO device service" as being synonymous with "IO
Space" accesses.
Click to expand...

Yawn. Pass the beernuts.


Kai
 
You confuse write-combine and write burst.

If a range in the bridge is set up for write combine, you can get
transactions out of order, and partial writes combined to one write.
If a range doesn't allow write-combine, you can still get a burst.
 
You confuse write-combine and write burst.
Click to expand...

Nope. I don't recall any bounds being placed on the definition of "burst" to
this point...Combining is synonymous with coalescing, and leads to a
multi-dataphase write transaction, which by any common definition is in fact
seen as a "burst" of data by the target agent...

/daytripper
 
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