There is a datasheet for the panel here. The 20 pin has LVDS with
three data pairs and a clock pair. And needs up to 5V @ 600mA on
the cable as well. Lamp powering is separate I guess. The three data
pairs carry 21 bits, of which 18 are color, leaving an Hsync, Vsync,
and a "DE".
http://www.ortodoxism.ro/datasheets/nec/NL10276BC28-05D.pdf
This is a datasheet for a 24 bit NEC panel. I wanted to see this, to verify
what the hardware interface looks like. This uses 4 data pairs and a
clock pair. 7 bits times 4 pairs, is 28 bits, of which 24 are the color
bits, leaving two static (undefined) signals, a reserved signal, and
"DE". I presume the 24 bit panel extracts Hsync and Vsync from the DE
signal somehow - not really sure.
http://www.esskabel.de/Datenblaetter/LCD-Specs/NEC/TFT/NL10276BC30-10...
Looking at the Intel 945GM datasheet, the LVDS interface only shows
three data pairs, and as near as I can tell, is intended for 18 bit
panels. Which makes me wonder why the Commell manual for the LV-677
shows four data pairs on the connector pinout ?
ftp://download.intel.com/design/mobile/datashts/30921903.pdf(945GM)
I'm guessing, when you made your cable, you connected ATX0, ATX1,
and ATX2 pairs to the panel ? JVLCD jumper set to 5 volts ? And been
extremely careful with the definition of pin one ? (Gotta watch
which view of the connector they are showing, and where the pin 1
actually is.)
When I look in the Commell downloadable BIOS, version 1.4, I see with
my hex editor, a module inside the BIOS called "cal_1284dvo.dat", and
my guess would be that it is the video BIOS included for the integrated
graphics. I notice the 945GM downloadable driver package, also includes
video BIOS files as separate files, and they have names with "cal_1413"
in them. The video BIOS is probably only important, if you wanted the
BIOS setup screen to be viewable on the flat panel. Otherwise, the
Windows driver would eventually display a picture of the Windows desktop,
if the video BIOS wasn't the right one.
Time to fire up that oscilloscope

You'll need 100 ohm diff termination
on the end of the cable for the clock pair and the data pair (i.e. if trying
to scope the end of the cable, or at the connector). LVDS uses
current source/sink drive, and the resistor termination across the
diff data pair, is necessary to convert the current flow, into a voltage.
The voltage is quite low amplitude. Then probe single ended with your
high bandwidth, light loading, FET probe. Probing the clock signal first,
would be the most satisfying choice. The driver would only enable
the LVDS, if the display was supposed to be active. The driver should
be "power optimized" and won't drive the LVDS, unless commanded to.
Isn't debugging fun

I've even had to do it, with a couple
managers looking over my shoulder
Found another doc. Might want to have a browse thru this - won't fix
your problem, but might provide a bit more background and references.
At least this explains what Intel was thinking, when they put a
3 pair data interface on the LVDS.
"Using 24-bpp LVDS Panels with Intel Mobile Chipsets for Embedded Applications"
http://www.intel.com/design/intarch/papers/315975.pdf
Paul