Next generation Opteron 1207 pins!

  • Thread starter Thread starter ykhan
  • Start date Start date
Wow and I thought 940 was a lot, IOW what AMD is going to do with all
these extra pins!
Click to expand...

Gotta hold the chips down somehow (lotsa grounds and Vdd). ;-)
 
from the said:
Wow and I thought 940 was a lot, IOW what AMD is going to do with all
these extra pins!
Click to expand...

Second core, perchance?? Well, you know, all the extra power, ground,
and data, to keep the second core fed and happy. 8>.
 
Second core, perchance?? Well, you know, all the extra power, ground,
and data, to keep the second core fed and happy. 8>.
Click to expand...

I don't see where the second core would cost any significant I/O.
Power/ground, certainly.

Actually, I'm still amazed at a 940pin package for $hundreds. Pins are
expen$ive (30ish years ago we used 1800 pin modules, at six-figures apiece).
 
Ed said:
Wow and I thought 940 was a lot, IOW what AMD is going to do with
all these extra pins!
Click to expand...

http://www.amdzone.net/modules.php?name=Sections&req=viewarticle&artid=56
http://www.amdzone.net/pics/cpus/dualcore/1stdemo/diagram.jpg

<quote>
Each CPU has a path to the system request interface, and through the
crossbar switch shares the same memory controller, and 3 HyperTransport
links. AMD feels that the single memory controller is able to handle
both CPU cores. They also feel that the HyperTransport bandwidth
provided by three full speed links is more than adequate. AMD documents
reveal that perhaps a 10% drop in performance due to the shared components.
</quote>

Could AMD want each core to have its own memory controller?
 
from the said:
I don't see where the second core would cost any significant I/O.
Power/ground, certainly.
Click to expand...

Depends whether you want each core to have it's own memory controller &
HT links I guess.
Actually, I'm still amazed at a 940pin package for $hundreds. Pins are
expen$ive (30ish years ago we used 1800 pin modules, at six-figures apiece).
Click to expand...

Economies of scale .. plus technical advances. Heck I remember when 64
pin (DIL) packages for UARTs were expensive because they had to be
ceramic, rather than plastic, and we were contemplating how to get past
-that- barrier. 8>.
 
GSV Three Minds in a Can said:
Second core, perchance?? Well, you know, all the extra power, ground,
and data, to keep the second core fed and happy. 8>.
Click to expand...

Well, they said they are going to be able to fit dual-cores within the
existing S940. But with S940, you only have one memory controller
feeding both cores. Maybe this next gen socket will allow for dual
independent memory controllers too? Also likely by that time they'll
be doing DDR2 too.

Yousuf Khan
 
Well, they said they are going to be able to fit dual-cores within the
existing S940. But with S940, you only have one memory controller
feeding both cores. Maybe this next gen socket will allow for dual
independent memory controllers too? Also likely by that time they'll
be doing DDR2 too.
Click to expand...

You mean a 256-bit-wide memory interface? Wow.
 
Depends whether you want each core to have it's own memory controller &
HT links I guess.
Click to expand...

Other than that's not what AMD has been saying, another few hundred pins
isn't enough to do what you propose. A single memory channel would take
more than a hundred I/O.
Economies of scale .. plus technical advances. Heck I remember when 64
pin (DIL) packages for UARTs were expensive because they had to be
ceramic, rather than plastic, and we were contemplating how to get past
-that- barrier. 8>.
Click to expand...

Sure. Note that we're still in ceramic. ;-)
 
Well, they said they are going to be able to fit dual-cores within the
existing S940. But with S940, you only have one memory controller
feeding both cores. Maybe this next gen socket will allow for dual
independent memory controllers too?
Click to expand...

I don't buy it. Add up the pins. 1207 isn't enough. Also remember the
articles about the "extra" port on the K8's memory switch, just sitting
there ready for another core.
Also likely by that time they'll be doing DDR2 too.
Click to expand...

Ok, why more I/O?
 
keith said:
Actually, I'm still amazed at a 940pin package for
$hundreds. Pins are expen$ive
Click to expand...

What was the old rule? A dime apiece? So?
These things aren't wirewrapped & potted.
AFAIK, current packaging is like ultra-high precision BGA
(30ish years ago we used 1800 pin modules, at six-figures apiece).
Click to expand...

Yeah, but you didn't make Millions of modules per year.
Economies of scale!

-- Robert
 
Depends whether you want each core to have it's own memory controller &
HT links I guess.
Click to expand...

No particularly good reason for each core to have their own HT links,
that just complicates things for basically no improvement in
performance. Even dedicated memory controllers are unlikely to be
worthwhile, Intel has demonstrated quite clearly with their Xeons that
two CPUs can share a single memory controller with very little loss in
performance vs. AMD's NUMA design.

Now, if they try to slap *4* cores on a single die, now that's another
matter altogether.

Still, my money is on those extra pins being almost entirely made up
of power and grounding pins.
 
What was the old rule? A dime apiece? So?
Click to expand...

Purchased, socketed, manufactured and tested, closer to a dollar
apiece.
These things aren't wirewrapped & potted.
;-)

AFAIK, current packaging is like ultra-high precision BGA
Click to expand...

X86 processors are still PGA. The marketing model still demands it.
Certainly BGA would be cheaper.
Yeah, but you didn't make Millions of modules per year.
Economies of scale!
Click to expand...

No, not millions per year, but a hundred per machine. Of course they
did get better at making them and the cost went down. What killed 'em
was when it dropped to a half-dozen per machine. The economy of scale
went all to hell. ;-)

~1K pins still amazes me. 1K balls, less so.
 
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