New A8N-SLI Dlx Memory Timings!

[edde]

I just updated my Asus A8N-SLI DeLuXE to the latest official 1003 bios.
I noticed 4 new memory timings available in the bios in addition to the
normal ones. Does anybody have any recommendations for timings for these:

Row Cycle Time (Trc)
Row Refresh Cycle Time (Trfc)
Write Recovery Time (Twr)
Read To Write Delay (Trwt)

I am currently running 2 x 512MB OCZ PC3200EL Dual Channel at 2-3-3-6 1T at
400mhz

 

[40 PC SOCKET SET]

I just updated my Asus A8N-SLI DeLuXE to the latest official 1003 bios.
I noticed 4 new memory timings available in the bios in addition to the
normal ones. Does anybody have any recommendations for timings for these:

Row Cycle Time (Trc)
Row Refresh Cycle Time (Trfc)
Write Recovery Time (Twr)
Read To Write Delay (Trwt)

I am currently running 2 x 512MB OCZ PC3200EL Dual Channel at 2-3-3-6 1T at
400mhz

Oddly enough, it does depend on the timings dictated by the RAM
manufacturers ;-)

You are playing with fire. Stop it.

Jon

 

[edde]

Oddly enough, it does depend on the timings dictated by the RAM
manufacturers ;-)

You are playing with fire. Stop it.

Jon

I emailed OCZ and they said the timings are determined by the SPD on the
memory and to use AUTO.
But, the SPD settings on theses modules is way slower than what the memory
is advertised (for instance, the basic SPD settings for this memory is
Cas2.5-3-3-9, but the advertised and actual timings are Cas2.0-3-3-6)

 

[RJT]

I emailed OCZ and they said the timings are determined by the SPD on the
memory and to use AUTO.
But, the SPD settings on theses modules is way slower than what the memory
is advertised (for instance, the basic SPD settings for this memory is
Cas2.5-3-3-9, but the advertised and actual timings are Cas2.0-3-3-6)

Those timings are different from the ones you posted above. Leave the
first mentioned timings alone.

Of the latter timings, the ones you mention as advertised, are the
standard CAS, RAS-to-CAS, RAS precharge and Active to precharge (tras)
timings. It is not uncommon that the memory allows faster timings than
those that are set in the SPD. So, memory with SPD timings of 2.5/3/3/9,
but advertised at 2/3/3/6 should work with the latter. Just try.

In my case, my memory's SPD sets the CAS to 3, but it's advertised to
work at 2.5, which it does. FWIW, I would set your modules to 2.5/3/3/9,
as setting the tras timing around 9-11 seems te be more effective, or so
anandtech says in a review.

The other timings are best left alone if you don't know what you are
playing with.

 

[edde]

In my case, my memory's SPD sets the CAS to 3, but it's advertised to work
at 2.5, which it does. FWIW, I would set your modules to 2.5/3/3/9, as
setting the tras timing around 9-11 seems te be more effective, or so
anandtech says in a review.

The other timings are best left alone if you don't know what you are
playing with.

Thanks.
The memory is advertised as Cas2-3-3-6, so that is what I'm using. No need
to drop to Cas2.5.
As far as changing the Tras, that apparently only applied to the Nforce2
boards and not Nforce4 boards.
I've tried both 6 and 9 and there isn't much difference anyway.

 

[RJT]

Thanks.
The memory is advertised as Cas2-3-3-6, so that is what I'm using. No need
to drop to Cas2.5.
As far as changing the Tras, that apparently only applied to the Nforce2
boards and not Nforce4 boards.
I've tried both 6 and 9 and there isn't much difference anyway.

Oops, I meant CAS 2 ofcourse.

 

[Paul]

I emailed OCZ and they said the timings are determined by the SPD on the
memory and to use AUTO.
But, the SPD settings on theses modules is way slower than what the memory
is advertised (for instance, the basic SPD settings for this memory is
Cas2.5-3-3-9, but the advertised and actual timings are Cas2.0-3-3-6)

Around page 82 of this document, there is a bit of info:
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF

Row Cycle Time (Trc) "Bits 7­4. RAS#-active to RAS#-active or auto
refresh of the same bank. Typically ~70 ns.
These bits are encoded as follows
(only 7­13 are valid; all others are reserved):

Row Refresh Cycle Time (Trfc)
"Bits 11­8. Auto-refresh-active to RAS#-active or RAS# auto-refresh.
0000b = 9 bus clocks
1111b = 24 bus clocks"

Write Recovery Time (Twr)
"Bit 28. Measures when the last write datum is safely registered
by the DRAM. It measures from the last data to precharge (writes
can go back-to-back).
0 = 2 bus clocks
1 = 3 bus clocks"

Read To Write Delay (Trwt)

"Bits 6­4. Specifies the read-to-write delay. This is not a
DRAM-specified timing parameter, but must be considered due to
routing latencies on the clock forwarded bus. It is counted from
the first address bus slot that was not associated with part of
the read burst. These bits are encoded as follows:
000b = 1 bus clocks ...
101b = 6 bus clocks
110b = reserved
111b = reserved"

So, at least Trwt, the best value is what the BIOS says it is.
It is presumably determined by the length of the busses used
on the motherboard.

There is a sample datasheet for a memory chip here:
http://download.micron.com/pdf/datasheets/dram/ddr/256MBDDRx4x8x16.pdf

Page 77 and page 79 show example waveforms. You can see in one
figure that Trc=Tras+Trp. Another figure shows Twr. Page 58 shows
some numeric examples.

Unless you are really motivated, and want to do more research,
I think "Auto" is still the best setting for these Maybe
someone, somewhere, has done a guide specifically for Athlon64...
There is a guide here, but these descriptions are a little on
the generic side (i.e. they are about as useful as my advice).

http://www.rojakpot.com/freebog.aspx

To a first order approximation, memory performance is determined
solely by clock rate. Cranking from DDR400 to DDR500 will do more
for you than any amount of fiddling with the parameters. (The
previous statement is true for memory operated >= DDR400 rates.
Slower memory operation does benefit from changing the memory
parameters. I've read that it has something to do with
pipelining, apparently. Pipelining, at high clock rates,
makes many of the parameters a non-issue.)

You can see some examples here:
http://www6.tomshardware.com/motherboard/20040119/index-09.html#application_benchmarks

So, you can adjust Tcas and Tras to rational values if you
want - there is nothing wrong with doing that. Just don't
expect a big change when you do it. Any difference will
be most visible in a memory benchmark program, but may be
almost invisible in real life situations.

Good luck,
Paul