Limitation of PCI

  • Thread starter Thread starter Man-wai Chang ToDie (+MS=V32B)
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Man-wai Chang ToDie (+MS=V32B)

http://arstechnica.com/old/content/2004/07/pcie.ars/3

*** begin quote ***

What this means in real life is that if you want to put more than five
PCI devices on a system, then you must use PCI-to-PCI bridge chips
configured in the following manner:
*** end quote ***

Is this real?

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Man-wai Chang ToDie (+MS=V32B) said:
http://arstechnica.com/old/content/2004/07/pcie.ars/3

*** begin quote ***

What this means in real life is that if you want to put more than five
PCI devices on a system, then you must use PCI-to-PCI bridge chips
configured in the following manner:
*** end quote ***

Is this real?
Click to expand...

I've done analog simulations for this. Yes, there is a limit.
(The more PCI loads, the shorter the length of the bus allowed.)

The PCI bus is an shared unterminated bus, and the reflections bounce
off the (open) end of the bus ("reflected wave switching"). Within a
clock cycle period, the reflections have to be absorbed, so that the
data can be sampled at a valid one or zero value, at the end of the cycle.
That constrains how long the bus can be, how many loads can be put on it,
and so on. It is a miracle of engineering, only in the sense that
people really don't know how ugly things work on there :-) Some
choice quotes from Dr. Howard Johnson.

http://www.sigcon.com/Pubs/news/2_28.htm

"As you can see, this bus is going to be full of compromises."

"The PCI bus in actual operation is not pretty, but it works."

By using point-to-point interconnect, and no bus sharing, PCI Express
is a vast improvement over the PCI bus.

The only thing that PCI has going for it, is you can make the chips
with even old fab setups. You don't need 45nm technology to make
PCI chips - you could make them with 2 micron CMOS if you wanted.
So virtually any operating fab facility in the world, could make
a PCI chip. With PCI Express, there is a bit more of a challenge
to making the pad driver - after all, the signal is running at
2.5Gbit/sec (due to 8b10b coding, this carries 250MB/sec data).

HTH,
Paul
 
Man-wai Chang ToDie (+MS=V32B) said:
http://arstechnica.com/old/content/2004/07/pcie.ars/3

*** begin quote ***

What this means in real life is that if you want to put more than five
PCI devices on a system, then you must use PCI-to-PCI bridge chips
configured in the following manner:
*** end quote ***

Is this real?
Click to expand...

I've done analog simulations for this. Yes, there is a limit.
(The more PCI loads, the shorter the length of the bus allowed.)

The PCI bus is an shared unterminated bus, and the reflections bounce
off the (open) end of the bus ("reflected wave switching"). Within a
clock cycle period, the reflections have to be absorbed, so that the
data can be sampled at a valid one or zero value, at the end of the cycle.
That constrains how long the bus can be, how many loads can be put on it,
and so on. It is a miracle of engineering, only in the sense that
people really don't know how ugly things work on there :-) Some
choice quotes from Dr. Howard Johnson.

http://www.sigcon.com/Pubs/news/2_28.htm

"As you can see, this bus is going to be full of compromises."

"The PCI bus in actual operation is not pretty, but it works."

By using point-to-point interconnect, and no bus sharing, PCI Express
is a vast improvement over the PCI bus.

The only thing that PCI has going for it, is you can make the chips
with even old fab setups. You don't need 45nm technology to make
PCI chips - you could make them with 2 micron CMOS if you wanted.
So virtually any operating fab facility in the world, could make
a PCI chip. With PCI Express, there is a bit more of a challenge
to making the pad driver - after all, the signal is running at
2.5Gbit/sec (due to 8b10b coding, this carries 250MB/sec data).

HTH,
Paul
 
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