Input leakage current is for each and every I/O pin
in an input state. It does not apply to supply pins.
Quiescent supply current would be the "leakage" into a
power supplying pin. I quickly looked at a couple DDR
DRAM chip datasheets, and it is not specified. I expect
the DRAM manufacturer wants you to keep the clock running,
whenever the device has power on it. CKE is used to gate
the clock and reduce device power.
Leakage current on a CMOS input pin can be positive or negative.
AFAIK (I'm not a silicon pad designer), the P and N channel
input impedance is extremely high. The leakage current
comes from the protection diodes and not the transistor
gates. One protection diode is tied to the positive rail,
the other diode tied to ground (or to a substrate generator).
Presumably the input leakage spec is related to how these
diodes leak, and the temperature condition for the chip
would be speced to maximize the leakage current (i.e. 70C
would max the leakage for the diodes, and the current
doubles for every 7C rise in temp).
In the good old days, someone invented the "IDDQ test" for
CMOS devices. Some smart person noticed that pure CMOS
devices had very little current flow through the supply
pins, if all inputs had defined voltages and no clock was
present. The factory could do a preliminary die sort, by
looking at how much leakage current flowed through the
supply pins, while the device was quiescent. If more than
0 microamps was flowing, then there must be a DC fault in
some internal gate(s) and the device could be discarded,
without wasting money on packaging it.
Things have changed a bit since the "IDDQ test" was invented.
Geometries are a lot smaller, and suddenly there is a
significant quiescent leakage on the newer technologies. I'm
not sure IDDQ is useful any more, as one faulty gate inside
a silicon die would cause a current flow that would be swamped
out by the magnitude of the leakage from the rest of the
normal gates.
In any case, I don't see a value in a DDR spec sheet for a
traditional IDDQ condition. It seems all the current consumption
specs are with the clock running ? That is what I think I'm
reading in the datasheet.
The lowest current condition I can find, is 4mA, and that appears
to be with CKE disabled, but the clock is still running. Your
"IDDQ" will be less than 4mA and greater than 0mA. You should
contact your local FAE (who can contact the factory for you),
and ask several questions:
1) Is it safe to have a DDR DRAM chip powered but with no
clock running ? (Of course all data is lost.)
2) Do I have to go through the JEDEC initialization sequence,
before turning off the clock, yet continuing to meet
valid Vih/Vil for all inputs, clock included ? In
other words, you might not be allowed to just raise
the rail voltage with the clock disabled and leave it
like that forever. The JEDEC initialization sequence
may make some difference to internal nodal states.
3) Is there is preferred parked state for the clock
(differential 1-0 or 0-1 state, or even some normally
illegal state like 1-1 or 0-0, achieved with weak
pullup or pulldown resistors) ?
4) Can your factory provide me with typical values of
IDDQ for the above stated conditions, such as my stated
pre-condition (2) above, or some particular clock state
as in (3) ?
It is possible there is at least one charge pump inside the
device, and that might have a leakage associated with it.
My wild-assed guess is the current into the device supply
rails will be greater than 0mA, even if the clock is turned
off. Also, some DRAM devices have internal voltage
regulators, which of course would trash your hopes of a
zero power consumption.
And if you are thinking of solving the problem by using
a MOSFET to turn off the power to the DRAM chip, think
again. The I/O pins can become a sneak path for large
currents to flow. In the old days, if we turned off the
power on one of our CMOS subsystems, so much power would
flow through the I/O signals between subsystems, that the
rails on the unpowered subsystem would rise enough for
the thing to keep running! You may find it quite difficult
to prevent the DRAM from using the juice. The protection
diodes on the inputs are the sneak path. If there are
series resistors on the protection diodes, the problem may
not be as severe as if the diodes are directly connected
between input and rails.
You're going to have lots of fun
Paul
