K8L details emerge

[Yousuf Khan]

Lessee what the highlights are:
-shared L3 cache
-quad-core
-independent voltage regulation of the cores as well as the northbridge
-48-bit addressing, 1GB page sizes
-official coprocessor support through an HTX connector.
-very flexible DDR2/DDR3/FBDIMM support
-memory mirroring
-data poisoning
-HT retry
-doubled FP units
-prefetch tweaks

AMD shows off details of K8L
"Next is memory. The new core will support 48-bit addressing and 1GB
pages. Cray and SGI will be very happy with this, until they hit that
memory wall again. There is also official co-processor support, strongly
hinted to be on a HTX card. The key here will be the platform is aware
of them vs having to hack them in."
http://www.theinquirer.net/?article=31761

Yousuf Khan

Yousuf Khan

 

[David Kanter]

Lessee what the highlights are:
-shared L3 cache
-quad-core
-independent voltage regulation of the cores as well as the northbridge
-48-bit addressing, 1GB page sizes
-official coprocessor support through an HTX connector.
-very flexible DDR2/DDR3/FBDIMM support
-memory mirroring
-data poisoning
-HT retry

-doubled FP units

I'd be careful, there are no indications that the K8L will have any
more execution units. Only that the execution bandwidth doubled to
2x128b SSE ops/cycle.

DK

 

[Ed]

Lessee what the highlights are:
-shared L3 cache
-quad-core
-independent voltage regulation of the cores as well as the northbridge
-48-bit addressing, 1GB page sizes
-official coprocessor support through an HTX connector.
-very flexible DDR2/DDR3/FBDIMM support
-memory mirroring
-data poisoning
-HT retry
-doubled FP units
-prefetch tweaks

AMD shows off details of K8L
"Next is memory. The new core will support 48-bit addressing and 1GB
pages. Cray and SGI will be very happy with this, until they hit that
memory wall again. There is also official co-processor support, strongly
hinted to be on a HTX card. The key here will be the platform is aware
of them vs having to hack them in."
http://www.theinquirer.net/?article=31761

Yousuf Khan

Yousuf Khan

0. Native quad core
1. Hypertransport up to 5.2GT/s
2. Better coherency
3. Private L2, shared L3 cache that scales up.
4. Separate power planes and pstates for north bridge and CPU
5. 128b FPUs - see 14,15
6. 48b virtual/physical addressing and 1GB pages
7. Support for DDR2, eventually DDR3
8. Support for FBD1 and 2 eventually
9. I/O virtualization and nested page tables
10. Memory mirroring, data poisoning, HT retry protocol support
11. 32B instead of 16B ifetch
12. Indirect branch predictors
13. OOO load execution - similar to memory disambiguation
14. 2x 128b SSE units
15. 2x 128b SSE LDs/cycle
16. Several new instructions

http://www.realworldtech.com/forums/index.cfm?action=detail&id=67239&threadid=67239&roomid=11