Intel to start producing 3-chip chipsets for Xeons

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Black Jack

http://www.anandtech.com/news/shownews.html?i=21695

They report that Intel might switchover to a three-chip model (in
contrast to the rest of the industry considering one-chip models to be
the panacea), which would make it a contratrarian move. It's generally
thought that having less chips increases economy.

The three chips of the chipset would be the TNB (RAM-controllerless
northbridge), XNB (RAM controller), and ICH5 (i/o hub southbridge).
The XNB and ICH5 would both hang off of the TNB, and the TNB would
directly connect to the Xeon MP. This roughly seems to mimick AMD's
design, as the TNB would be roughly equivalent to an Opteron
Hypertransport link, while XNB would be roughly an Opteron RAM
controller. But of course this would be all external to the Xeons,
unlike in the Opterons. Also it looks like having the XNB hanging off
of the TNB would make the TNB extremely busy, handling both i/o coming
in from RAM and from peripherals; just like it does these days, so I
don't see where either economy or performance are to be had.

However, I do see that separating out the RAM controller might allow
them to attach multiple RAM controllers in an attempt to mimick the
scaling that multi-Opterons have. However, having the RAM controller
on a separate chip might increase the number of hops between RAM and
CPU, thus increasing latency. So a good solution for RAM bandwidth,
but a bad solution for RAM latency, perhaps?

Yousuf Khan
 
http://www.anandtech.com/news/shownews.html?i=21695

They report that Intel might switchover to a three-chip model (in
contrast to the rest of the industry considering one-chip models to be
the panacea), which would make it a contratrarian move. It's generally
thought that having less chips increases economy.
Click to expand...

"moving to a three chip model"? say what?

So...the Lindenhurst MCH, PXH, and Hanse Rapids ICH for Nocona are chopped
liver?

/daytripper (you really should find better sources than "Toms"...)
 
daytripper said:
"moving to a three chip model"? say what?

So...the Lindenhurst MCH, PXH, and Hanse Rapids ICH for Nocona are chopped
liver?
Click to expand...

Actually, it was Anands, not Toms. :-)

Anyways, they were talking about Xeon MPs not Xeon DPs, so it wouldn't
be about Noconas but about Potomacs instead.

Yousuf Khan
 
Actually, it was Anands, not Toms. :-)

Anyways, they were talking about Xeon MPs not Xeon DPs, so it wouldn't
be about Noconas but about Potomacs instead.
Click to expand...

Intel doesn't currently make any XeonMP chipsets, so they can't really
be "moving" to a new technology! But as Daytrippper mentions, 3-chips
or more is the norm for their server chipsets. Their E7505 XeonDP
chipset is 3 chips, the MHC, PCH/PXH and ICH. Their Itanium chipset
uses a whole whack of chips (anywhere from 5 up to 11 chips for a 4P
server... no wonder Itanium2 motherboards are so much more expensive
than Opteron boards!).

Even if we're just looking at current XeonMP chipsets, the only option
available now is the Broadcom Serverworks GC-HE, and that is a 3-chip
solution (REMC for memory, CIBO-X for PCI-X and CSB5 for legacy I/O).
 
Intel doesn't currently make any XeonMP chipsets, so they can't really
be "moving" to a new technology! But as Daytrippper mentions, 3-chips
or more is the norm for their server chipsets. Their E7505 XeonDP
chipset is 3 chips, the MHC, PCH/PXH and ICH. Their Itanium chipset
uses a whole whack of chips (anywhere from 5 up to 11 chips for a 4P
server... no wonder Itanium2 motherboards are so much more expensive
than Opteron boards!).

Even if we're just looking at current XeonMP chipsets, the only option
available now is the Broadcom Serverworks GC-HE, and that is a 3-chip
solution (REMC for memory, CIBO-X for PCI-X and CSB5 for legacy I/O).
Click to expand...

We have a winner.

Intel killed their quad Xeon chipset in favor of having Serverworks "do it for
them" (so to speak). The Serverworks GC-HE is the chipset I used for our quad
server (Foster/Gallatin) design - almost two years ago. ie: It's old. It's
400mhz FSB only. But then so are the Fosters and Gallatins ;-)

(GC-LE - using CMIC-LE - for the dualies goes to 533mhz fsb, fwiw)

Also fwiw: The GC-HE core chipset actually consisted of:

- CMIC (their "MCH")
- CIOB (their "PXH" - which came in multiple flavors)
- CSB5 (quasi "ICH")
- and finally the REMC memory interface slice (of which you actually had to
use at least 3 - one for the address/control function and a pair of data slice
functions).

That's a minimum of 6 chipset parts and more typically 8 parts (5 REMCs for a
full-capacity-but-not-mirrored-memory platform). That's a lot of parts...

Back to the original posit (where ever it came from): being fair, one *could*
make the argument that a Hanse Rapids behind the Linderhurst-VS MCH is all it
takes to do a dual Xeon 800mhz fsb design with modest PCI bus support.

So if we *had* been talking about dual Xeons, it *is* possible to do them with
only two Intel chipset components, even if the result isn't exactly what most
might want to buy...

cheers

/daytripper
 
daytripper said:
Even if we're just looking at current XeonMP chipsets, the only option
available now is the Broadcom Serverworks GC-HE, and that is a 3-chip
solution (REMC for memory, CIBO-X for PCI-X and CSB5 for legacy I/O).
Click to expand...

We have a winner.

Intel killed their quad Xeon chipset in favor of having Serverworks "do it for
them" (so to speak). The Serverworks GC-HE is the chipset I used for our quad
server (Foster/Gallatin) design - almost two years ago. ie: It's old. It's
400mhz FSB only. But then so are the Fosters and Gallatins ;-) [...]
Also fwiw: The GC-HE core chipset actually consisted of:

- CMIC (their "MCH")
- CIOB (their "PXH" - which came in multiple flavors)
- CSB5 (quasi "ICH")
- and finally the REMC memory interface slice (of which you actually had to
use at least 3 - one for the address/control function and a pair of data slice
functions).

That's a minimum of 6 chipset parts and more typically 8 parts (5 REMCs for a
full-capacity-but-not-mirrored-memory platform). That's a lot of parts...
Click to expand...

Well, except that it looks like it can have up to 3 CIOBs, I would
expect the "typical" configuration to have at least 2, for 9 parts?

Hmm, SuperMicro actually documents roughly how they wired some of
their motherboards, take the P4QH6/P4QH8 for example... It has 2
CIOB-X giving them 9 chips in the chipset part, and a host of other
chips to provide other functions (network, graphic, SCSI, "Super IO").
(the manual even shows how everything is connected!)

I counted to 13 major chips, most of them with lots of pin, and then
there's the CPU, VRM's and PCI-X slots... Combined with the much lower
volume it's no wonder why server boards costs money!

http://www.supermicro.com/PRODUCT/MotherBoards/GC_HE/P4QH6.htm
http://www.supermicro.com/PRODUCT/Manuals/MB/GC-HE/P4QH8-6_1.0a.pdf
http://www.supermicro.com/product/superserver/mec2.htm

The corresponding Tyan (Thunder GC-HE) looks similar, it also uses
2xCIOB-X, but it has 2xIntel 82550 network controllers instead but
supports less memory (not sure if that reduces the number of REMC).

http://www.tyan.com/products/html/thundergche_spec.html
ftp://ftp.tyan.com/datasheets/d_s4520_180.pdf
ftp://ftp.tyan.com/manuals/m_s4520_101.pdf
 
daytripper said:
Even if we're just looking at current XeonMP chipsets, the only option
available now is the Broadcom Serverworks GC-HE, and that is a 3-chip
solution (REMC for memory, CIBO-X for PCI-X and CSB5 for legacy I/O).
Click to expand...

We have a winner.

Intel killed their quad Xeon chipset in favor of having Serverworks "do it for
them" (so to speak). The Serverworks GC-HE is the chipset I used for our quad
server (Foster/Gallatin) design - almost two years ago. ie: It's old. It's
400mhz FSB only. But then so are the Fosters and Gallatins ;-) [...]
Also fwiw: The GC-HE core chipset actually consisted of:

- CMIC (their "MCH")
- CIOB (their "PXH" - which came in multiple flavors)
- CSB5 (quasi "ICH")
- and finally the REMC memory interface slice (of which you actually had to
use at least 3 - one for the address/control function and a pair of data slice
functions).

That's a minimum of 6 chipset parts and more typically 8 parts (5 REMCs for a
full-capacity-but-not-mirrored-memory platform). That's a lot of parts...
Click to expand...

Well, except that it looks like it can have up to 3 CIOBs, I would
expect the "typical" configuration to have at least 2, for 9 parts?
Click to expand...

You'd have to do a survey to know what the actual "typical" GC-HE
configuration is, but the point was not what the maximum number of core
chipset parts one could use was, but what the *minimum* parts required was.

(And that a three-chip set really isn't a crime against humanity after all ;-)

/daytripper
 
Black said:
http://www.anandtech.com/news/shownews.html?i=21695

They report that Intel might switchover to a three-chip model (in
contrast to the rest of the industry considering one-chip models to be
the panacea), which would make it a contratrarian move. It's generally
thought that having less chips increases economy.

The three chips of the chipset would be the TNB (RAM-controllerless
northbridge), XNB (RAM controller), and ICH5 (i/o hub southbridge).
The XNB and ICH5 would both hang off of the TNB, and the TNB would
directly connect to the Xeon MP. This roughly seems to mimick AMD's
design, as the TNB would be roughly equivalent to an Opteron
Hypertransport link, while XNB would be roughly an Opteron RAM
controller. But of course this would be all external to the Xeons,
unlike in the Opterons. Also it looks like having the XNB hanging off
of the TNB would make the TNB extremely busy, handling both i/o coming
in from RAM and from peripherals; just like it does these days, so I
don't see where either economy or performance are to be had.

However, I do see that separating out the RAM controller might allow
them to attach multiple RAM controllers in an attempt to mimick the
scaling that multi-Opterons have. However, having the RAM controller
on a separate chip might increase the number of hops between RAM and
CPU, thus increasing latency. So a good solution for RAM bandwidth,
but a bad solution for RAM latency, perhaps?

Yousuf Khan
Click to expand...
Actually they are XMB's not XNB's
Eric
 
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