Intel and Hypertransport?

[nobody]

Even though The Inquirer' articles should be taken with a grain of
salt, they might be up to something here:
http://www.theinquirer.net/?article=27317
See also http://www.theinquirer.net/?article=1685
In fact, after so many flops, especially on Xeon front, the best way
out for Intel may be to swallow it, and license socket940 from AMD (or
maybe their cross-licensing agreement already gives Intel the rights
to use it). Also good for consumers - that would create first shared
platform since the days of socket7.

NNN

 

[YKhan]

In fact, after so many flops, especially on Xeon front, the best way
out for Intel may be to swallow it, and license socket940 from AMD (or
maybe their cross-licensing agreement already gives Intel the rights
to use it). Also good for consumers - that would create first shared
platform since the days of socket7.

Actually, Intel and AMD's cross-licensing specifically excludes data
bus technologies. That's why AMD had to stop making Intel
pin-compatible processors after the K6. Now it's time for AMD to make
Intel beg for access.

But anyways, Intel's problems simply go way beyond what bus technology
that they are using. If Intel were to license Socket 940 from AMD, that
would mean not only would it have to build in Hypertransport
(relatively simple), but also a memory controller. Intel simply doesn't
seem to know how to integrate a memory controller into their CPUs,
despite all of their years of integrating one into their chipsets. You
could point out that they should know how to integrate memory
controllers into processors from their Timna experience, but let's face
it Timna was a cancelled processor, there must've been a reason for it
to be cancelled. And even with the Hypertransport, they won't have
access to the coherent HT that is the real secret behind building
multi-socket server chips.

 

[George Macdonald]

In fact, after so many flops, especially on Xeon front, the best way
out for Intel may be to swallow it, and license socket940 from AMD (or
maybe their cross-licensing agreement already gives Intel the rights
to use it). Also good for consumers - that would create first shared
platform since the days of socket7.

Actually, Intel and AMD's cross-licensing specifically excludes data
bus technologies. That's why AMD had to stop making Intel
pin-compatible processors after the K6. Now it's time for AMD to make
Intel beg for access.

Remember that since then, there was the cross-license agreement of May 2001
http://contracts.corporate.findlaw.com/agreements/amd/intel.license.2001.01.01.html
- it's impossible to figure exactly what was included in that agreement due
to deleted confidential clauses in the public version but it's safe to
assume it did cover Intel's use of 64-bit extensions and AMDs use of SSEx.
Hypertransport is also an open standard and it would appear anybody can
join for a few $$. That said, even if Intel were to adopt HT, which I
seriously doubt, it'd be highly unlikely that they'd adopt the exact same
socket and pin-out.

 

[nobody]

In fact, after so many flops, especially on Xeon front, the best way
out for Intel may be to swallow it, and license socket940 from AMD (or
maybe their cross-licensing agreement already gives Intel the rights
to use it). Also good for consumers - that would create first shared
platform since the days of socket7.

Actually, Intel and AMD's cross-licensing specifically excludes data
bus technologies. That's why AMD had to stop making Intel
pin-compatible processors after the K6. Now it's time for AMD to make
Intel beg for access.

But anyways, Intel's problems simply go way beyond what bus technology
that they are using. If Intel were to license Socket 940 from AMD, that
would mean not only would it have to build in Hypertransport
(relatively simple), but also a memory controller. Intel simply doesn't
seem to know how to integrate a memory controller into their CPUs,
despite all of their years of integrating one into their chipsets. You
could point out that they should know how to integrate memory
controllers into processors from their Timna experience, but let's face
it Timna was a cancelled processor, there must've been a reason for it
to be cancelled. And even with the Hypertransport, they won't have
access to the coherent HT that is the real secret behind building
multi-socket server chips.

AFAIR, Timna died because of Rambus being unpopular and too expensive
for low-end "value" systems it was intended for, and inability of
Intel to get the stop-gap MTH (or whatever else they called that
Rambus-to-SDRAM chip) right. Timna was Rambus-only since its
conception because back then Intel was arrogantly thinking that the
market would swallow anything Intel was pushing on it, including
Rambus. There was nothing wrong with Timna as such, except that it
didn't fit into the market niche it was intended for.

As for access to the coherent HT, AMD may sell it for the right price.
The common platform might make easier access for AMD to the markets
now closed to them (think Dell). OTOH that may be the reason Intel
will not go for it.

NNN

 

[Del Cecchi]

In fact, after so many flops, especially on Xeon front, the best way
out for Intel may be to swallow it, and license socket940 from AMD (or
maybe their cross-licensing agreement already gives Intel the rights
to use it). Also good for consumers - that would create first shared
platform since the days of socket7.

Actually, Intel and AMD's cross-licensing specifically excludes data
bus technologies. That's why AMD had to stop making Intel
pin-compatible processors after the K6. Now it's time for AMD to make
Intel beg for access.

But anyways, Intel's problems simply go way beyond what bus technology
that they are using. If Intel were to license Socket 940 from AMD, that
would mean not only would it have to build in Hypertransport
(relatively simple), but also a memory controller. Intel simply doesn't
seem to know how to integrate a memory controller into their CPUs,
despite all of their years of integrating one into their chipsets. You
could point out that they should know how to integrate memory
controllers into processors from their Timna experience, but let's face
it Timna was a cancelled processor, there must've been a reason for it
to be cancelled. And even with the Hypertransport, they won't have
access to the coherent HT that is the real secret behind building
multi-socket server chips.

AFAIR, Timna died because of Rambus being unpopular and too expensive
for low-end "value" systems it was intended for, and inability of
Intel to get the stop-gap MTH (or whatever else they called that
Rambus-to-SDRAM chip) right. Timna was Rambus-only since its
conception because back then Intel was arrogantly thinking that the
market would swallow anything Intel was pushing on it, including
Rambus. There was nothing wrong with Timna as such, except that it
didn't fit into the market niche it was intended for.

As for access to the coherent HT, AMD may sell it for the right price.
The common platform might make easier access for AMD to the markets
now closed to them (think Dell). OTOH that may be the reason Intel
will not go for it.

NNN

Intel wouldn't have to license HT unless they wanted interoperability
with chipsets for some reason. They could do their own coherent source
synchronous point to point link. It's a little tricky but not that hard.

del

 

[keith]

In fact, after so many flops, especially on Xeon front, the best way
out for Intel may be to swallow it, and license socket940 from AMD (or
maybe their cross-licensing agreement already gives Intel the rights
to use it). Also good for consumers - that would create first shared
platform since the days of socket7.

Actually, Intel and AMD's cross-licensing specifically excludes data
bus technologies. That's why AMD had to stop making Intel
pin-compatible processors after the K6. Now it's time for AMD to make
Intel beg for access.

But anyways, Intel's problems simply go way beyond what bus technology
that they are using. If Intel were to license Socket 940 from AMD, that
would mean not only would it have to build in Hypertransport
(relatively simple), but also a memory controller. Intel simply doesn't
seem to know how to integrate a memory controller into their CPUs,
despite all of their years of integrating one into their chipsets. You
could point out that they should know how to integrate memory
controllers into processors from their Timna experience, but let's face
it Timna was a cancelled processor, there must've been a reason for it
to be cancelled. And even with the Hypertransport, they won't have
access to the coherent HT that is the real secret behind building
multi-socket server chips.

AFAIR, Timna died because of Rambus being unpopular and too expensive
for low-end "value" systems it was intended for, and inability of
Intel to get the stop-gap MTH (or whatever else they called that
Rambus-to-SDRAM chip) right. Timna was Rambus-only since its
conception because back then Intel was arrogantly thinking that the
market would swallow anything Intel was pushing on it, including
Rambus. There was nothing wrong with Timna as such, except that it
didn't fit into the market niche it was intended for.

As for access to the coherent HT, AMD may sell it for the right price.
The common platform might make easier access for AMD to the markets
now closed to them (think Dell). OTOH that may be the reason Intel
will not go for it.

NNN

Intel wouldn't have to license HT unless they wanted interoperability
with chipsets for some reason. They could do their own coherent source
synchronous point to point link. It's a little tricky but not that hard.

del

When Opteron was released Intel said, the on-die memory controller and
HT bus is a short lived stop-gap for AMD, it won't get them far, every
chip will need diff ram and boards, bla bla bla, then went on to say
something about how they'll have a better solution that will expand for
at least 10 years.

What gets me is that any engineer worth salt sees this as *obvious*. WTF
is INtel thinking (actually we know; Itanic).

Hmmmm must of just been Intel trying to calm their investors down. ;p Ed

....and trying to sell a $10B pig.

 

[EdG]

In fact, after so many flops, especially on Xeon front, the best way
out for Intel may be to swallow it, and license socket940 from AMD (or
maybe their cross-licensing agreement already gives Intel the rights
to use it). Also good for consumers - that would create first shared
platform since the days of socket7.

Actually, Intel and AMD's cross-licensing specifically excludes data
bus technologies. That's why AMD had to stop making Intel
pin-compatible processors after the K6. Now it's time for AMD to make
Intel beg for access.

But anyways, Intel's problems simply go way beyond what bus technology
that they are using. If Intel were to license Socket 940 from AMD, that
would mean not only would it have to build in Hypertransport
(relatively simple), but also a memory controller. Intel simply doesn't
seem to know how to integrate a memory controller into their CPUs,
despite all of their years of integrating one into their chipsets. You
could point out that they should know how to integrate memory
controllers into processors from their Timna experience, but let's face
it Timna was a cancelled processor, there must've been a reason for it
to be cancelled. And even with the Hypertransport, they won't have
access to the coherent HT that is the real secret behind building
multi-socket server chips.

AFAIR, Timna died because of Rambus being unpopular and too expensive
for low-end "value" systems it was intended for, and inability of
Intel to get the stop-gap MTH (or whatever else they called that
Rambus-to-SDRAM chip) right. Timna was Rambus-only since its
conception because back then Intel was arrogantly thinking that the
market would swallow anything Intel was pushing on it, including
Rambus. There was nothing wrong with Timna as such, except that it
didn't fit into the market niche it was intended for.

As for access to the coherent HT, AMD may sell it for the right price.
The common platform might make easier access for AMD to the markets
now closed to them (think Dell). OTOH that may be the reason Intel
will not go for it.

NNN

Intel wouldn't have to license HT unless they wanted interoperability
with chipsets for some reason. They could do their own coherent source
synchronous point to point link. It's a little tricky but not that hard.

del

When Opteron was released Intel said, the on-die memory controller and
HT bus is a short lived stop-gap for AMD, it won't get them far, every
chip will need diff ram and boards, bla bla bla, then went on to say
something about how they'll have a better solution that will expand for
at least 10 years.

Hmmmm must of just been Intel trying to calm their investors down. ;p
Ed

 

[Tony Hill]

Intel wouldn't have to license HT unless they wanted interoperability
with chipsets for some reason. They could do their own coherent source
synchronous point to point link. It's a little tricky but not that hard.

Yup, and they would probably call it "Common Serial Interconnect" and
use it for both their "Tigerton" Xeon processors and their "Tukwila"
Itanium processors, to be released in 2007 and 2008 respectively.

I'm not really sure what the guys at The Inquirer were smoking when
they wrote their article, because they seem to have totally mixed up
what chip was supposed to use which bus. The chip that Intel
canceled, "Whitefield" was NOT going to use CSI, instead using a more
legacy-style shared bus. It's successor, codenamed "Tigerton" was
supposed to be the same core as "Whitefield" but using an integrated
memory controller and CSI to connect to the rest of the world.

Regardless of what codenames are used, the basic point is quite
simple, Intel has full plans on developing their own
hypertransport-like serial interconnect for future processors.

 

[EdG]

Regardless of what codenames are used, the basic point is quite
simple, Intel has full plans on developing their own
hypertransport-like serial interconnect for future processors.

It'll sure be interesting to see what Intel comes out with, but it'll
have to be better then what AMD has now, rumors going around say AMD's
M2 socket will run @ 333MHz instead of todays 200MHz, HT bandwidth is
increased, the on-die memory controller supports DDR2 and DDR3 ram,
plus other tweaks to bring down latency even more.

Can't wait for the fun to start!
Ed

 

[Del Cecchi]

In fact, after so many flops, especially on Xeon front, the best way
out for Intel may be to swallow it, and license socket940 from AMD
(or
maybe their cross-licensing agreement already gives Intel the rights
to use it). Also good for consumers - that would create first
shared
platform since the days of socket7.

Actually, Intel and AMD's cross-licensing specifically excludes data
bus technologies. That's why AMD had to stop making Intel
pin-compatible processors after the K6. Now it's time for AMD to
make
Intel beg for access.

But anyways, Intel's problems simply go way beyond what bus
technology
that they are using. If Intel were to license Socket 940 from AMD,
that
would mean not only would it have to build in Hypertransport
(relatively simple), but also a memory controller. Intel simply
doesn't
seem to know how to integrate a memory controller into their CPUs,
despite all of their years of integrating one into their chipsets.
You
could point out that they should know how to integrate memory
controllers into processors from their Timna experience, but let's
face
it Timna was a cancelled processor, there must've been a reason for
it
to be cancelled. And even with the Hypertransport, they won't have
access to the coherent HT that is the real secret behind building
multi-socket server chips.

AFAIR, Timna died because of Rambus being unpopular and too
expensive
for low-end "value" systems it was intended for, and inability of
Intel to get the stop-gap MTH (or whatever else they called that
Rambus-to-SDRAM chip) right. Timna was Rambus-only since its
conception because back then Intel was arrogantly thinking that the
market would swallow anything Intel was pushing on it, including
Rambus. There was nothing wrong with Timna as such, except that it
didn't fit into the market niche it was intended for.

As for access to the coherent HT, AMD may sell it for the right
price.
The common platform might make easier access for AMD to the markets
now closed to them (think Dell). OTOH that may be the reason Intel
will not go for it.

NNN

Intel wouldn't have to license HT unless they wanted interoperability
with chipsets for some reason. They could do their own coherent
source
synchronous point to point link. It's a little tricky but not that
hard.

del

When Opteron was released Intel said, the on-die memory controller and
HT bus is a short lived stop-gap for AMD, it won't get them far, every
chip will need diff ram and boards, bla bla bla, then went on to say
something about how they'll have a better solution that will expand
for
at least 10 years.

What gets me is that any engineer worth salt sees this as *obvious*.
WTF
is INtel thinking (actually we know; Itanic).

Hmmmm must of just been Intel trying to calm their investors down. ;p
Ed

...and trying to sell a $10B pig.

What is obvious to any engineer on a low salt diet.? You lost me on that
one.

The bus structure on Itanic means little with respect to market
acceptance, it seems to me.

del

 

[keith]

On Mon, 31 Oct 2005 21:45:40 -0600, "Del Cecchi"

In fact, after so many flops, especially on Xeon front, the best way
out for Intel may be to swallow it, and license socket940 from AMD
(or
maybe their cross-licensing agreement already gives Intel the rights
to use it). Also good for consumers - that would create first
shared
platform since the days of socket7.

Actually, Intel and AMD's cross-licensing specifically excludes data
bus technologies. That's why AMD had to stop making Intel
pin-compatible processors after the K6. Now it's time for AMD to
make
Intel beg for access.

But anyways, Intel's problems simply go way beyond what bus
technology
that they are using. If Intel were to license Socket 940 from AMD,
that
would mean not only would it have to build in Hypertransport
(relatively simple), but also a memory controller. Intel simply
doesn't
seem to know how to integrate a memory controller into their CPUs,
despite all of their years of integrating one into their chipsets.
You
could point out that they should know how to integrate memory
controllers into processors from their Timna experience, but let's
face
it Timna was a cancelled processor, there must've been a reason for
it
to be cancelled. And even with the Hypertransport, they won't have
access to the coherent HT that is the real secret behind building
multi-socket server chips.

AFAIR, Timna died because of Rambus being unpopular and too
expensive
for low-end "value" systems it was intended for, and inability of
Intel to get the stop-gap MTH (or whatever else they called that
Rambus-to-SDRAM chip) right. Timna was Rambus-only since its
conception because back then Intel was arrogantly thinking that the
market would swallow anything Intel was pushing on it, including
Rambus. There was nothing wrong with Timna as such, except that it
didn't fit into the market niche it was intended for.

As for access to the coherent HT, AMD may sell it for the right
price.
The common platform might make easier access for AMD to the markets
now closed to them (think Dell). OTOH that may be the reason Intel
will not go for it.

NNN

Intel wouldn't have to license HT unless they wanted interoperability
with chipsets for some reason. They could do their own coherent
source
synchronous point to point link. It's a little tricky but not that
hard.

del


When Opteron was released Intel said, the on-die memory controller and
HT bus is a short lived stop-gap for AMD, it won't get them far, every
chip will need diff ram and boards, bla bla bla, then went on to say
something about how they'll have a better solution that will expand
for
at least 10 years.

What gets me is that any engineer worth salt sees this as *obvious*.
WTF
is INtel thinking (actually we know; Itanic).

Hmmmm must of just been Intel trying to calm their investors down. ;p
Ed

...and trying to sell a $10B pig.

What is obvious to any engineer on a low salt diet.? You lost me on that
one.

Low salt diet? I said worth the salt paid! You folks short of salt out
there in MN land?

The bus structure on Itanic means little with respect to market
acceptance, it seems to me.

It has nothing to do with Itanic's bus structure at all, rather the
Intel *MARKETEERS* who decided that Itanic was all the "future" we
needed, thus all we caould have. AMD's engineers (well worth their salt,
IMO) decided otherwise and made the point rather loudly, perhaps because
their marketters had different motives than those who favored Itanic.

 

[Del Cecchi]

keith wrote:
snip

Low salt diet? I said worth the salt paid! You folks short of salt out
there in MN land?

Got plenty, but it is all imported from kansas and places like that.

It has nothing to do with Itanic's bus structure at all, rather the
Intel *MARKETEERS* who decided that Itanic was all the "future" we
needed, thus all we caould have. AMD's engineers (well worth their salt,
IMO) decided otherwise and made the point rather loudly, perhaps because
their marketters had different motives than those who favored Itanic.

I still don't know what was supposed to be obvious. That Itanium is not
doing well in the marketplace and Intel strategy seems to be failing?
That FSB is going to be replaced by a network? That Hypertransport is
wonderful?

There are all sorts of things that are obvious but don't seem to be so.
Blue baskets, amsround, all that. (internal IBM stuff)

 

[Keith]

keith wrote:
snip

Got plenty, but it is all imported from kansas and places like that.
I still don't know what was supposed to be obvious. That Itanium is not
doing well in the marketplace and Intel strategy seems to be failing?

Sure. Evolution beats revolution, once again (FS all over again).

That FSB is going to be replaced by a network? That Hypertransport is
wonderful?

It's only "wonderful" in the sense that it's not an FSB.

There are all sorts of things that are obvious but don't seem to be so.
Blue baskets, amsround, all that. (internal IBM stuff)

What about AMSROUND wasn't so? ISTR it being the (ugly) truth.

 

[YKhan]

I'm not really sure what the guys at The Inquirer were smoking when
they wrote their article, because they seem to have totally mixed up
what chip was supposed to use which bus. The chip that Intel
canceled, "Whitefield" was NOT going to use CSI, instead using a more
legacy-style shared bus. It's successor, codenamed "Tigerton" was
supposed to be the same core as "Whitefield" but using an integrated
memory controller and CSI to connect to the rest of the world.

The CSI, yes, but not the integrated memory controller, no. Now
Tigerton will use neither. The revamped Tigerton just replaces
Whitefield completely, including using the FSB and shared memory
controller. However, it might have dual FSB's, and connect one FSB to
the memory controller, while the other FSB connects to I/O.

Regardless of what codenames are used, the basic point is quite
simple, Intel has full plans on developing their own
hypertransport-like serial interconnect for future processors.

Yes, after a few delays, obviously.

Yousuf Khan

 

[YKhan]

It'll sure be interesting to see what Intel comes out with, but it'll
have to be better then what AMD has now, rumors going around say AMD's
M2 socket will run @ 333MHz instead of todays 200MHz, HT bandwidth is
increased, the on-die memory controller supports DDR2 and DDR3 ram,
plus other tweaks to bring down latency even more.

You mean the Hypertransport is running at 333Mhz instead of 200Mhz? I
didn't realize that that was what their real Mhz ratings were.

As for the new on-die memory controller, I heard DDR2, but didn't hear
that it was also already setup for DDR3? Has DDR3 gotten finalized
already?

Yousuf Khan

 

[Del Cecchi]

Sure. Evolution beats revolution, once again (FS all over again).




It's only "wonderful" in the sense that it's not an FSB.




What about AMSROUND wasn't so? ISTR it being the (ugly) truth.

Both were true. But apparently not obvious, at least to the bigwigs.
It was an early "Jam" only without management involvement.

 

[keith]

Both were true. But apparently not obvious, at least to the bigwigs.

Intel's bigs didn't "get" Itanic/AMD64 either. I'm not sure they have
yet.

It was an early "Jam" only without management involvement.

....which is why I don't "jam". If they really wanted the information it's
there to be had.

Think about it this way; IBM "got" their customers' message WRT FS,
some thirty years ago (which is why zOS is still with us). Intel didn't
"got" the message at all, even though both were as loud as Barbara
Streisand's nose. It took AMD to "got" them the message. ...and I'm not
convinced they've "got" it yet. All I see is panic.

 

[Tony Hill]

You mean the Hypertransport is running at 333Mhz instead of 200Mhz? I
didn't realize that that was what their real Mhz ratings were.

They aren't really, or at least not normally in PC applications.
200MHz is the default speed for hypertransport links on their initial
startup, but then the two sides of the link negotiate the maximum
speed at which they can operate (potentially being different in each
directly). In PCs use the Hypertransport clock is usually run at
800MHz or 1000MHz (DDR for 1600MT/s or 2000MT/s respectively).

What the original poster may be thinking of is the transmit clock used
to generate the Hypertransport clock. In most applications both ends
of the hypertransport link use a single clock to synchronize to. They
will then use an internal multiplier to generate their Hypertransport
clock off of this sync clock. In PC use the standard is to use a
200MHz transmit clock to both the chipset and the CPU in order to sync
everything up.

Of course, changing this transmit clock isn't really going to benefit
much of anything. As long as you can easily multiply that clock up to
whatever speed you need there should be no problems. No data is
actually sent with that sync clock, so nothing much should change.

Really the only place that this clock comes into play is when trying
to overclock your system. If, for example, you run your sync clock at
210MHz on a system where everything assumes a transmit clock of 200MHz
then you will overclock everything (processor core speed, HT speed and
memory speed at least) by 5%. However if the system is designed for a
333MHz transmit clock right from the get-go then you're right back
where you started. Then you would need to bump that clock up to
350MHz to get the same 5% overclock.

As far as I know there are no plans on changing this sync clock speed
because really, 200MHz just makes sense as a sync clock for
Hypertransport. The same holds true for Hypertransport 2.0.

 

[George Macdonald]

You mean the Hypertransport is running at 333Mhz instead of 200Mhz? I
didn't realize that that was what their real Mhz ratings were.

I think he's possibly referring to the base system clock which is fed to
the CPU clock circuits & the I/O chip clock buffer for PCI, AGP etc.
Current BIOS Setups have a HT multiplier setting which has a max of x5 in
mbrds I've seen, giving the 1000MHz which becomes 2000MT/s with DDR. The
333MHz makes sense in that it'd take HT to its original stated max design
speed of 3200MT/s in each direction and allow DDR2 clocking without
changing the CPU clock circuit's multipliers & dividers.