I/O address (system resources)

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esara

Hi
I am trying to understand a subjec which titled "System Resources"! in
this chapter they are trying to explanin IRQ, DMA, I/O devices
(address). I have had hard time to follow what the author want to say
(please see belwo).

What I thought that if a user is trying to click the mouse then an IRQ
of the mouse will be activated and this signal will make the CPU to
jump to the memory part that support to communication with the mouse,
now if the CPU want to say somthing to mouse then he will write that
command in that memory and then (somehow) this command will be sent to
the mouse...

Now what I do not understand exactly from the description below is
that they are saying that the CPU will send an address (in this case,
mouse address) and this address will be listened by all the i/o
devices?? why is that?? since the CPU got the IRQ from the mouse, the
the CPU must be known that this is a mouse so he will go to that part
of memory that support the mouse and somehow the command will go to
that mouse after the address of the mouse is activated.

Am I right?? if not could you please help me to understand this
concept?? I have found it it is hard to understand that book.. thanks
a lot in advace for the help indeed.

====================
<quote>
I/O address
Numbers assigned to hardware devices that softwarew use to send a
command to adevice. Each device "listens" for these numbers and
responds to the ones assigned to it.
</quote>

In another page with a diagram it is mentioned the following steps

<quote>
I/O address
1) CPU turns up signal on bus that says "I/O address are on the
address line"
2) All I/O devices controllers listen for their address
3) CPU transmits an I/O address
4) The device that "own" the address responds
</quote>
 
Hi
I am trying to understand a subjec which titled "System Resources"! in
this chapter they are trying to explanin IRQ, DMA, I/O devices
(address). I have had hard time to follow what the author want to say
(please see belwo).

What I thought that if a user is trying to click the mouse then an IRQ
of the mouse will be activated and this signal will make the CPU to
jump to the memory part that support to communication with the mouse,
now if the CPU want to say somthing to mouse then he will write that
command in that memory and then (somehow) this command will be sent to
the mouse...

Now what I do not understand exactly from the description below is
that they are saying that the CPU will send an address (in this case,
mouse address) and this address will be listened by all the i/o
devices?? why is that?? since the CPU got the IRQ from the mouse, the
the CPU must be known that this is a mouse so he will go to that part
of memory that support the mouse and somehow the command will go to
that mouse after the address of the mouse is activated.

Am I right?? if not could you please help me to understand this
concept?? I have found it it is hard to understand that book.. thanks
a lot in advace for the help indeed.
Click to expand...

Kind of, except in the architecture of a PC, it has separate address
space for I/O, so if it needs to communicate with a port, it
communicates to the I/O addresses either assigned to it under PNP, or
it is manually set to (either hard wired or set by jumpers).
====================
<quote>
I/O address
Numbers assigned to hardware devices that softwarew use to send a
command to adevice. Each device "listens" for these numbers and
responds to the ones assigned to it.
</quote>
Click to expand...

That is inaccrurate. The way it really is is there is a huge range of
addresses, and each device is set (as above, either by PNP,
hardwired, or jumpers), to respond to a small range in the entier I/O
range.
In another page with a diagram it is mentioned the following steps

<quote>
I/O address
1) CPU turns up signal on bus that says "I/O address are on the
address line"
2) All I/O devices controllers listen for their address
3) CPU transmits an I/O address
4) The device that "own" the address responds
</quote>
Click to expand...

Not quite.

The CPU sets the address, sets the AEN (address enable line, tells
devices there is a valid address on the bus)., then IOR or IOW. IOR
tells the device to output data for the CPU to read, IOW tells the
device the CPU has data for it.
 
Gary said:
Kind of, except in the architecture of a PC, it has separate address
space for I/O, so if it needs to communicate with a port, it
communicates to the I/O addresses either assigned to it under PNP, or
it is manually set to (either hard wired or set by jumpers).



That is inaccrurate. The way it really is is there is a huge range of
addresses, and each device is set (as above, either by PNP,
hardwired, or jumpers), to respond to a small range in the entier I/O
range.




Not quite.

The CPU sets the address, sets the AEN (address enable line, tells
devices there is a valid address on the bus)., then IOR or IOW. IOR
tells the device to output data for the CPU to read, IOW tells the
device the CPU has data for it.
Click to expand...
Then, after the OS loads, and is running, in RAM, there is also this
thing called 'polling'...
 
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