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Dueling announcements: Intel vs. IBM-alliance on metal & high-K
E
Ed
I was sort of surprised by this....(if true)....
Intel will not counter AMD's approach to create a native, single-chip
quad-core processor and continue to produce the quad-core Penryn in a
dual-die, multi-chip package instead.
Single-die quad-cores are not expected to arrive until the introduction
of the Nehalem core, which will succeed Penryn with a completely new 45
nm architecture in the second half of 2008.
http://www.tgdaily.com/2007/01/27/intel_45nm_penryn_details/
R
Robert Myers
Will be one of the more interesting chapters in the history of
technology, if it works.
Robert.
Y
Yousuf Khan
Ed said:Intel will not counter AMD's approach to create a native, single-chip
quad-core processor and continue to produce the quad-core Penryn in a
dual-die, multi-chip package instead.
Single-die quad-cores are not expected to arrive until the introduction
of the Nehalem core, which will succeed Penryn with a completely new 45
nm architecture in the second half of 2008.
http://www.tgdaily.com/2007/01/27/intel_45nm_penryn_details/
I'm a bit surprised at that, they were talking about native quad-core in
the same time-frame as AMD's native quad-core.
However, it might take them longer to implement native-quad-core, since
they'd have to redesign the L2 cache to be shared by 4 cores rather than
just 2. AMD is going with a shared L3 cache instead, so it might be a
bit more flexible in its placement and design.
Yousuf Khan
Y
Yousuf Khan
Robert said:Will be one of the more interesting chapters in the history of
technology, if it works.
Robert.
Why is this supposed to be such a big deal as compared to some of the
other developments from years gone by, like copper interconnects, and
SOI, and strain?
Yousuf Khan
D
David Kanter
Why is this supposed to be such a big deal as compared to some of the
other developments from years gone by, like copper interconnects, and
SOI, and strain?
The magnitude and impact of the improvements and because without it,
Moore's Law would have gotten ugly.
I strongly urge you to read pages 2-4:
http://www.realworldtech.com/page.cfm?ArticleID=RWT012707024759
Basically without high k and metal, transistor scaling would have been
severely compromised. You couldn't really improve performance without
more power and losing density. Now you can for the next couple of
generations.
DK
D
Del Cecchi
Yousuf Khan said:Why is this supposed to be such a big deal as compared to some of the
other developments from years gone by, like copper interconnects, and
SOI, and strain?
Yousuf Khan
And as I recall, most of those things were played down by Intel. I
certainly remember negative comments about copper and soi.
R
Robert Myers
Why is this supposed to be such a big deal as compared to some of the
other developments from years gone by, like copper interconnects, and
SOI, and strain?
Becuase it gives you two things you want at the same time: reduced
power consumption and faster operation--goals that had come to seem
mutually incompatible. From my perspective, the reduced power
consumption is the more important one. The main constraint on the
kind of computing that interests me most is computational density,
which is in turn constrained by power consumption. This is really
good news for computational physics.
SOI, copper interconnect and even strained silicon seem possible to
understand without a deep understanding of solid state physics. The
ideas may not be obvious, but they seem at least natural. All the
natural ideas, though, seemed to have pretty well run their course,
and it looked like the chip alchemists were out of tricks.
Not so, apparently, and for reasons I think I'll have to do an awful
lot of reading to understand. At the moment, it looks like a game-
changer.
Robert.
D
Del Cecchi
dood, it's simple. using poly silicon and silicon dioxide works reallyRobert Myers said:Becuase it gives you two things you want at the same time: reduced
power consumption and faster operation--goals that had come to seem
mutually incompatible. From my perspective, the reduced power
consumption is the more important one. The main constraint on the
kind of computing that interests me most is computational density,
which is in turn constrained by power consumption. This is really
good news for computational physics.
SOI, copper interconnect and even strained silicon seem possible to
understand without a deep understanding of solid state physics. The
ideas may not be obvious, but they seem at least natural. All the
natural ideas, though, seemed to have pretty well run their course,
and it looked like the chip alchemists were out of tricks.
Not so, apparently, and for reasons I think I'll have to do an awful
lot of reading to understand. At the moment, it looks like a game-
changer.
Robert.
well until the oxide thickness is so thin that tunneling (you remember
tunneling right? that heisenberg thing?) causes a bunch of leakage right
through the supposed gate insulator. Now if you had a gate insulator
that had a higher dielectric constant you could make it thicker, take out
the tunneling, and still have the same electric field at the silicon
surface. And if the gate material were something with a different work
function then you could make the insulator even thicker. Ta Da. QED etc.
The hard part is finding something that you can actually use to build
real transistors in a manufacturing environment.
It ain't the phyics, exactly. Its the chemistry and the mechanics.
del
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Robert Myers
Let's see. You can tell me if this is wrong. To make the channel
conducting, you have to move a certain amount of charge, q, to the
vicinity of the gate, in effect, charging the capacitor that is the
made by the channel, the insulating layer, and the gate electrode.
q=CV. Lower C means higher V, meaning (I am guessing) that you have
to raise the gate voltage, something you don't want. Thickening the
insulating layer lowers C, a higher dielectric constant raises it.
Higher dielectric constant allows you to thicken the layer of
insulation without lowering C.
What had me confused is that it had seemed to me that gate capacitance
is something you *don't* want, since the time to charge the gate is
the fundamental limit to the speed of operation of the transistor.
Finally I realized that the amount of charge you have to move is a
property of the conducting channel and not of the gate. At least, if
I've got the story straight.
Robert.
conducting, you have to move a certain amount of charge, q, to the
vicinity of the gate, in effect, charging the capacitor that is the
made by the channel, the insulating layer, and the gate electrode.
q=CV. Lower C means higher V, meaning (I am guessing) that you have
to raise the gate voltage, something you don't want. Thickening the
insulating layer lowers C, a higher dielectric constant raises it.
Higher dielectric constant allows you to thicken the layer of
insulation without lowering C.
What had me confused is that it had seemed to me that gate capacitance
is something you *don't* want, since the time to charge the gate is
the fundamental limit to the speed of operation of the transistor.
Finally I realized that the amount of charge you have to move is a
property of the conducting channel and not of the gate. At least, if
I've got the story straight.
Robert.
D
Del Cecchi
Yes, that is pretty much the way I understand it. The charge is
necessary to invert the channel, that is have enough minority carriers
to make a layer of material look like it has become the opposite of what
it usually is. ie, change P type material to N type.
There is a lot of stuff with bands and potential wells if you are so
inclined. But that is basically it.
As for the gate capacitance, there is overlap capacitance and fringing
fields etc that are other components that don't go into inverting the
channel.
necessary to invert the channel, that is have enough minority carriers
to make a layer of material look like it has become the opposite of what
it usually is. ie, change P type material to N type.
There is a lot of stuff with bands and potential wells if you are so
inclined. But that is basically it.
As for the gate capacitance, there is overlap capacitance and fringing
fields etc that are other components that don't go into inverting the
channel.
Y
Yousuf Khan
And as I recall, most of those things were played down by Intel. I
certainly remember negative comments about copper and soi.
Exactly.
Yousuf Khan