Dothan vs. Turion test

  • Thread starter Thread starter Yousuf Khan
  • Start date Start date
Y

Yousuf Khan

Here's the start page:
http://www.laptoplogic.com/resources/detail.php?id=17&page=1

Here's the conclusions page:
http://www.laptoplogic.com/resources/detail.php?id=17&page=16

It looks like Dothan's TDP is only 75% of its real maximum power
consumption, while AMD's is 100%. Therefore even in a heavy load
situation, Pentium-M doesn't ever get to its full maximum power
consumption, and it seems to last longer. But Turion seems to last
longer under light to average loads.
Our original hypothesis about Turion was that it would be more power efficient under idle usage circumstances, like the Life test in Winstone's BatteryMark test. Since the Life test consists of running common productivity applications with timed periods of idle-ness to simulate true user interaction, Turion's architecture lends itself to being more efficient. First, the power ratings between Dothan and Turion cannot be directly compared. A lot of people see Dothan's 27W TDP & Turion ML's 35W TDP and assume that Dothan is automatically lower power. Intel computes thermal design power as 75% of the maximum load on the chip, while AMD's TDP rating is derived from the absolute worst case power dissipation of the chip. Part of the total system power is also incorporated into AMD's TDP, as the memory controller is located on-chip. Intel's memory controller is built into the chipset and thus draws power not calculated as part of Dothan's TDP. Also while Turion 64 is at idle (800M
Click to expand...
Hz clock speed), it's performance is likely to be higher due to the higher bandwidth data bus. All of these factors contribute to Turion 64 being more power efficient under low load circumstances.
 
THe author of that article was most likely off his rocker. AMD's
microarchitecture has much lower IPC than the Pentium M. In fact, the
difference in IPC between the Pentium M and the K8 is about the same as
the difference between the K8 and the P4.

DK
 
Kimmy said:
A bit old, no?

Dated August 30, 2005
Click to expand...

No, the article was revisited and updated over time. It reappeared in a
news search recently. At least one of the updates was in Sept 2005. And
perhaps some small changes in Dec 2005 made it reappear in the searches.

Yousuf Khan
 
David said:
THe author of that article was most likely off his rocker. AMD's
microarchitecture has much lower IPC than the Pentium M. In fact, the
difference in IPC between the Pentium M and the K8 is about the same as
the difference between the K8 and the P4.
Click to expand...

The K8's pipeline has only been increased from K7, from 10 to 12
stages, the same as the difference between the Pentium-M and Pentium-3.
(Pentium-M supposedly has somewhere between 12 and 14 stages).

Yousuf Khan
 
YKhan said:
The K8's pipeline has only been increased from K7, from 10 to 12
stages, the same as the difference between the Pentium-M and Pentium-3.
(Pentium-M supposedly has somewhere between 12 and 14 stages).
Click to expand...

I fail to see how this is in any way related to the point I made.

My comment:

IPC(PM) - IPC(K8) ~ IPC(K8) - IPC(P4E)

That's measured IPC.

Your comment:

K8 pipeline is 12 stages.

I fail to see the connection, or the point.

DK
 
THe author of that article was most likely off his rocker. AMD's
microarchitecture has much lower IPC than the Pentium M. In fact, the
difference in IPC between the Pentium M and the K8 is about the same as
the difference between the K8 and the P4.
Click to expand...

Do you have a source for nunbers on this please? Both K8 and P-M are
improvements over PIII and P4 is a degradation in terms of IPC. While I'll
believe Intel has improved P-M over what AMD has done -- one would hope
thay could in all that time, albeit without 64-bit yet -- I quite frankly
dispute your contention that ratios of IPC for K8:P4 and P-M:K8 are even
close.
 
David said:
I fail to see how this is in any way related to the point I made.
Click to expand...

The number of pipeline stages is strongly correlated with IPC; it may
not be a linear correlation, but it could be a logarithmic one. The K7
and P3 were the same number of pipeline stages, and very nearly the same
IPC. The P4 had twice (and eventually thrice) as many pipeline stages
and had much worse IPC than either of them. If we consider P3/K7 to be
the baselines, then their derived processors should be comparable too.
So a K8, derived from K7, and a P-M, derived from a P3, should be
comparable with each other given that their pipelines were increased
about the same amount.
My comment:

IPC(PM) - IPC(K8) ~ IPC(K8) - IPC(P4E)

That's measured IPC.
Click to expand...

Measured? By whom?

Yousuf Khan
 
David said:
I fail to see how this is in any way related to the point I made.
Click to expand...


The number of pipeline stages is strongly correlated with IPC; it may
not be a linear correlation, but it could be a logarithmic one. The K7
and P3 were the same number of pipeline stages, and very nearly the same
IPC. The P4 had twice (and eventually thrice) as many pipeline stages
and had much worse IPC than either of them. If we consider P3/K7 to be
the baselines, then their derived processors should be comparable too.
So a K8, derived from K7, and a P-M, derived from a P3, should be
comparable with each other given that their pipelines were increased
about the same amount.
My comment:

IPC(PM) - IPC(K8) ~ IPC(K8) - IPC(P4E)

That's measured IPC.
Click to expand...


Measured? By whom?

Yousuf Khan
 
I fail to see how this is in any way related to the point I made.

My comment:

IPC(PM) - IPC(K8) ~ IPC(K8) - IPC(P4E)

That's measured IPC.
Click to expand...

Just how, pray tell, are you measuring IPC here?!? MIPS and FLOPS?
Some other synthetic measure? Real world applications? And if the
latter, just WHICH applications are you using to give your definitive
measure of IPC?
 
Back
Top