J
joeu2004
My system has a 2.13 GHz Pentium-M CPU. That means a clock cycle is
about 0.469 nsec.
Does that mean that the best-case performance of a "1 cycle"
instruction (e.g. MOV reg,reg) is 0.469 nsec (!)?
(Just considering u-pipe execution, and ignoring cache misses and
other latency factors.)
Or is "2.13 GHz" some microcycle clock rate, and it takes some number
(how many?) microcycles to equal an instruction clock cycle?
I am surprised because I can remember when the TTL turn-on time was on
the order of 5 nsec. I know component technology has improved
dramatically, but wow!
Also, in the Old Days, it was not unusual to spec a CPU clock rate
that was much higher than the instruction rate. (But those were CISC,
not RISC, CPUs.)
(Actually, I just did the math, and perhaps I should not be surprised,
considering a common corollary of Moore's Law that applies to
performance.)
about 0.469 nsec.
Does that mean that the best-case performance of a "1 cycle"
instruction (e.g. MOV reg,reg) is 0.469 nsec (!)?
(Just considering u-pipe execution, and ignoring cache misses and
other latency factors.)
Or is "2.13 GHz" some microcycle clock rate, and it takes some number
(how many?) microcycles to equal an instruction clock cycle?
I am surprised because I can remember when the TTL turn-on time was on
the order of 5 nsec. I know component technology has improved
dramatically, but wow!
Also, in the Old Days, it was not unusual to spec a CPU clock rate
that was much higher than the instruction rate. (But those were CISC,
not RISC, CPUs.)
(Actually, I just did the math, and perhaps I should not be surprised,
considering a common corollary of Moore's Law that applies to
performance.)