They are called I/O addresses and every device that uses them
should have a unique value. The reason you have more than
one option, is for resource juggling - if another device
has a fixed allocation, devices that have multiple values can
be configured to use a non-conflicting value.
As for the concept of I/O, everything these days is memory
mapped. That means the processor address bus is decoded by
hardware logic, to identify just the particular register
in a device you are after. IOW, the hardware looks like
a chunk of ram, and the processor doesn't do anything
different when accessing DRAM, as opposed to some chip
register. They are all accessed with load or store
instructions.
Even today, a processor with an Intel instruction set has
to support I/O instructions. The "IN" and "OUT" instructions
are examples of I/O instructions. Think of this as a legacy
way for the processor to read/write the hardware.
http://faydoc.tripod.com/cpu/in.htm
http://faydoc.tripod.com/cpu/out.htm
Looking at a Z80 family datasheet, an I/O instruction
almost looks like a load/store, except that the IORQ
signal gets asserted during the bus transaction. I guess
that makes the IORQ into a 33rd address bit. The timing
on the bus is also different, because the design intent
was to access hardware devices that don't perform the
same way as a memory.
I wish I could remember more about this, but as I've
thrown out all the docs I had on this stuff, it is hard
to look up, and also hard to find the old info on the
web. The information predates PDF versions or Postscript
versions of documents, and many times the books were
only printed and not in an electronic form.
HTH,
Paul
