T
ThierryBingo
hey,
I have two questions regarding the cache and code optimisation and
woul appreciate your help
1- Do current compilers interchange nested loops order to minimise
page fault as well as cache fault? for instance if the arrays are
stored in row order, the following code
for (i = 0; i < 100; i++)
for (j = 0; j < 100; j++)
x[j] = x[j]+3;
will perform much better than
for (j = 0; j < 100; j++)
for (i = 0; i < 100; i++)
x[j] = x[j]+3;
do the current widely used compilers (c++, java) perform such
optimisation automatically?
2- Write Through on write HIT
according to Patterson book: with this policy the data is written in
the cache and the lower-level memory.
my first question if we have two levels caching. will the write be
done in L1, L2 and the physical DRAM or just L2 while using this
write policy?
my second question is related to the book evaluation to the technique.
he says that the processor will be held up on writes unless they are
buffered. I don't clearly understand what he means. my understanding
is that with this policy the data is sent to the cache AND the lower
memory level AT THE SAME TIME. no? if yes, how will this policy hold
the processor back ?unless he means that while writing the data to the
off chip memory the data bus is used and no data can be read from the
DRAM?
thanks for your help
I have two questions regarding the cache and code optimisation and
woul appreciate your help
1- Do current compilers interchange nested loops order to minimise
page fault as well as cache fault? for instance if the arrays are
stored in row order, the following code
for (i = 0; i < 100; i++)
for (j = 0; j < 100; j++)
x[j] = x[j]+3;
will perform much better than
for (j = 0; j < 100; j++)
for (i = 0; i < 100; i++)
x[j] = x[j]+3;
do the current widely used compilers (c++, java) perform such
optimisation automatically?
2- Write Through on write HIT
according to Patterson book: with this policy the data is written in
the cache and the lower-level memory.
my first question if we have two levels caching. will the write be
done in L1, L2 and the physical DRAM or just L2 while using this
write policy?
my second question is related to the book evaluation to the technique.
he says that the processor will be held up on writes unless they are
buffered. I don't clearly understand what he means. my understanding
is that with this policy the data is sent to the cache AND the lower
memory level AT THE SAME TIME. no? if yes, how will this policy hold
the processor back ?unless he means that while writing the data to the
off chip memory the data bus is used and no data can be read from the
DRAM?
thanks for your help