Jerry said:
To clear the CMOS setting of my mobo, I have to move the jumper cap from
pin 1-2 to 2-3, but in the mobo manual, it said "Except when clearing
the RTC RAM, never remove the cap on CLRTC jumper default position.
Removing the cap will cause system boot failure."
Anybody knows why the removing the cap will cause system boot failure.
Actually what will be observed in this case?
The cap could be a power path for the CMOS well.
The CMOS well is a chunk of circuitry inside the Southbridge chip.
It includes the RTC (real time clock) and the 128 or 256 byte CMOS
RAM. It may also include logic for some of the power management
states, handling PME or whatever. For example, if you have WOL
(wake on LAN), something in the Southbridge has to be awake to
listen to it.
This is a possible design.
+5VSB (from PSU) ---- 5V_to_3V_regulator ---- diode --+
|
Battery (CR2032 3V) -- 1Kohm_resistor ------- diode --+
|
1 X
2 X----> to Southbridge
and CMOS well...
3 X
|
Ground
When the computer is running or in standby, +5VSB powers
the circuit. If the computer is switched off at the back,
or the computer is unplugged, the CR2032 battery is used.
The current drawn from the battery is small enough, that
the battery will last for three years if the computer is
unplugged.
The diodes prevent reverse current flow, and prevent the
battery from being charged. If the battery started to
charge, it would explode. The CR2032 is not designed for
charging.
Now, consider the jumper scheme, shown as a 1x3 header in
this case. If the jumper is missing, the CMOS well gets
no power. If the computer is started in that state, the
RTC is dead, and so is the CMOS RAM. While there are
supposed to be things like transmission gates, to isolate
the well, getting garbage when those two subsystems are
read out, cannot help. And if there is any power management
logic in the well, it would be toast, and the system might
not be able to start, if the power management said "go
back to sleep".
If the jumper is in position 2-3, that drains the accumulated
charge on any bypass caps on the CMOS well voltage. Position
2-3 causes the power in the well to drop to zero, and also
drains nodes in the CMOS gates themselves (eventually).
If the jumper is in position 1-2, then the well is powered at
all times. The RTC clock continues to run, and the CMOS RAM
contents are maintained.
That is not the only way to design the circuit. There are CMOS
jumper schemes with only pins 1-2, a 1x2 header. An Intel
Southbridge, for example, has a CMOS reset pin, so that
you don't have to interrupt the power to the circuit to
clear the CMOS contents. So there are other ways to do it.
I've drawn the circuit above, to match your description.
One of the other ways of drawing that circuit, *requires*
that the computer be unplugged/powered off, before a CMOS
reset. For safety, it is generally suggested that you unplug
the computer, to guarantee that the 5V_to_3V regulator is
not running. If the regulator is running, the computer is
plugged in, and the place where the two diodes join is grounded,
that *burns* one of the diodes. For that reason, I always warn
people to unplug the computer, before fooling with the circuit.
As drawn above, that circuit does not have the problem - the
diode cannot burn as drawn above. But one of the other ways of
drawing the circuit, will burn it. And that way of doing it,
was quite popular. The 1K ohm resistor in the battery path,
is a current limiter, so that no more than 3mA can flow from
the battery. They cannot place a resistor in the upper leg,
as when the computer is running, the well could have
some dynamic current consumption, so the upper path is
"hard", and capable of providing enough current to burn
the diode. When the PSU is powered off or unplugged, there
is no longer a source of +5VSB.
+5VSB (from PSU) ---- 5V_to_3V_reg -- diode --+
|
Battery (CR2032 3V) -- 1Kohm -------- diode --+--+---> to Southbridge
| and CMOS well...
1 X
(Short points 1 and 2 together,
to clear the CMOS. Computer 2 X
should be unplugged.) |
ground
HTH,
Paul
