This might be what AMD is using to fill the capacity at Fab 30 while it
converts it to Fab 38.
AMD to make GPUs in Dresden fab
http://www.theinquirer.net/default.aspx?article=33320
Tony said:I doubt that we'll see much, if any, ATI chips produced at AMD fabs
this year, but it only makes sense for AMD to eventually start
building the chips there. My personal guess (based mainly on
gut-instinct) is that they'll start with the motherboard chipsets and
then work out from there. High-end graphics parts are probably at
least a year away from being produced in AMD fabs.
Two years. ATI has never targeted an SOI process, and they'd need to
start using whatever CAD tools AMD uses internally. That's a pretty
big shift, and it's not something you'd ever do in the middle of a
project...
Considering that GPUs take at least 3 years to design, I think the
earliest that this could happen is 2 years from now (assuming that
there is a design that started 6-12 months ago, and was still in
architectural phase and hadn't done any actual physical stuff).
There is no law that says ANMD *must* do SOI in Dresden.
Even if
they wanted to go with the current process, it's not that big of a
shift, at least for the logic designers.
Pick one set of "books"
instead of another. Circuit design is different (presumably AMD
already has the necessary circuits), and processing is different,
but one logic chip looks pretty much like the next.
It would take less than a year to migrate a design form bulk to a
mature SOI process.
My rough
estimate is that the design time for a GPU is 3 years, and PD probably
starts after 1 year. After they start PD, I don't think they'd
retarget.
Why 3 years though? It seems like nVidia and ATI are pushing out new
cores every 12 to 15 months. When nVidia got their asses whopped
during the FX5xxx series (late 02/ early 03), they pretty much took
only about a year to answer with the FX6xxx (Apr 2004), then the
FX7xxx (Jun 2005). It seems that they must necessarily change their
design after their concept with the FX5xxx bombed and that would give
only 2 years at most between that and the 7xxx series.
David said:Two years. ATI has never targeted an SOI process, and they'd need to
start using whatever CAD tools AMD uses internally. That's a pretty
big shift, and it's not something you'd ever do in the middle of a
project...
This might be what AMD is using to fill the capacity at Fab 30 while it
converts it to Fab 38.
AMD to make GPUs in Dresden fab
http://www.theinquirer.net/default.aspx?article=33320
Well considering that AMD has stated they will be doing 'copy exact'...
Yes, but if you've already started on any PD, you're going to need to
redo that. I think from a project management standpoint it would be a
pretty bad idea.
I would expect that if they wanted to switch over
they would start with designs that haven't done much PD. My rough
estimate is that the design time for a GPU is 3 years, and PD probably
starts after 1 year. After they start PD, I don't think they'd
retarget.
AMD has the necessary circuits, but ATI engineers have no experience
with them. That's just asking for trouble, even if you have AMD
circuits guys coaching them along. Delays for CPUs are bad, but for
GPUs they are brutal, since the life time is so much shorter.
Can you elaborate? Do you mean a design that is already in bulk
production? Or do you just mean a taped out bulk design?
semiconductor. Although I don't know if they're using SOI or bulk wafers
for these chips, that fab is a SOI fab.
krw said:One can do bulk CMOS on a line already set up for SOI, is my point.
This "bad idea" has been done before.
Have you ever *done* this? Me thinks you're talking though your
hat, again.
One doesn't need "experience" with a circuit to use it.
Logic is
logic, fer chrissake. The biggest problem with SOI is getting the
circuit designs right.
Either way. Assuming no silicon (though metal changes may be
necessary) respins for logic errors, to SOI production volumes.
This would include hardware verification and perhaps two passes
(engineering then production) through silicon. The switch may be
transparent for a design already in the pipe, though logic errors
are an issue on a new design.
I don't know enough to evaluate whether that is true or not.
However, if you did bulk, you'd have to fully characterize that process, to get
all the physical parameters you want for design.
When and where? Did they hit their release targets?
Were there any yield issues?
No I haven't, I'm not an EE. If you have a timeline you'd like to
suggest, go ahead...
I don't really buy this argument. Mainly because you are going to be
constantly tweaking your circuits to get better performance, lower
power or ideally both. That means you have to know what is going on in
circuit land...
And yields...
Also, how big a design are we talking about? GPUs are not as tricky as
CPUs, but they are some of the larger and more complex ASICs out
there...
If you are saying you can port a SCSI controller from bulk to SOI in a
year, then I'm not sure that means much. I'm hoping you are talking
about a substantial design...
Just because you release a product every 12-15 months doesn't mean it
only takes 12-15 months to design. Think about pipelining...
Intel has been releasing new cores every 2-3 years (Willamette,
Prescott, Conroe), but it is quite well known that design takes 5
years. How can that happen? Multiple design teams. Who says ATI and
Nvidia don't have multiple design teams?
IBM. I'm not going to get into specifics.
I already did. Less than a year, assuming a good design.
Of course you don't buy into reality. Logic designers don't tweak
circuits. They select books the circuit designers have already
qualified. One doesn't go messing with circuits once the logic is
cast. Can you say "chase your tail"?
Remember, AMD has a mature SOI process. The yield thing isn't part
of the equation.
My experience is with CPUs, so calibrate from there. According to
your assumption, migrating a GPU to SOI is a walk in the park.
Now really, a SCSI controller in SOI would be rather silly, no?
krw said:One can do bulk CMOS on a line already set up for SOI, is my point.
One doesn't need "experience" with a circuit to use it. Logic is
logic, fer chrissake. The biggest problem with SOI is getting the
circuit designs right.
David said:I think you're putting words in my mouth.
I'm saying that generally CPUs are more complex than GPUs; certainly an
ARM7 isn't as complex as the most modern GPU, but...as a general rule
of thumb, a CPU is going to be more complex than a GPU.
I would agree that porting a GPU to SOI should be easier than porting a
CPU, especially since *on average* you have less custom design work.
However, I think characterizing either as 'trivial' is silly.
David said:I'll ask if it was a SOI device...
Is there no common stages between bulk and SOI that require slightly
different variations of a tool? What I mean is that the purpose of the
processing stage may be the same in either case, but due to the
differences between bulk and SOI, you have to buy one version of a tool
for bulk but another version of the tool for SOI.
Isn't ATI's Xbox360 chipset already produced at Singapore's Chartered
Semi? That would likely make it SOI wouldn't it?
[snip]
So you won't say whether or not it turned out to be a horrible idea?
What constitutes a 'good design'?
So what happens if your target frequency is say, 600MHz, and it turns
out you can only hit 400MHz, but you have 3-4 months before tape out?
Do you just sit on your ass and let the circuits moulder? Or do you,
perhaps, start tweaking things to get improvements, track down critical
paths and fix them?
Or do you perhaps go back to the logic guys and say: "Hey, you blew a
lot of timing on this one chunk, could we try something quicker..."
I'm not really that sure. Acceptable yields for a 100mm^2 die may be
unreasonable for a 350mm^2 die, especially considering that GPUs have a
much higher density of logic, which is going to be more vulnerable to
defects. For a CPU, you at least have a pretty good chance of hitting
cache, which is easy to fix.
I think you're putting words in my mouth.
I'm saying that generally CPUs are more complex than GPUs; certainly an
ARM7 isn't as complex as the most modern GPU, but...as a general rule
of thumb, a CPU is going to be more complex than a GPU.
I would agree that porting a GPU to SOI should be easier than porting a
CPU, especially since *on average* you have less custom design work.
However, I think characterizing either as 'trivial' is silly.
Sure, but I don't know what kind of design you were working on, and you
haven't chosen to share that information. Therefore, I can't really
come to any conclusions about whether your experience porting is
closely correlated to that of a GPU, a lower bound, an upper bound,
etc...
In other words, I need more info!