"Art C." said:
Hello Group,
It has come to my attention when using all 4 memory slots on the A8V Deluxe
rev2.0 with decent DDR400 memory some AMD64 cpu's like the Winchester core
will back down to 333mhz and not utilize dual channel. Now I hear if I
upgrade to the new AMD64 Venice core the system will run dual channel at
400mhz.
But when I talked with AMD's tech support and asked if I skip the Venice
upgrade and wait for the new 64X2 cpu's will they support using all 4-slots
like the Venice core, he was stomped. Has anyone found any tech notes on
the new 64X2 MANCHESTER or TOLEDO core about this subject?
Thanks for some input,
Art C.
I see little reason for this "the next processor will be a better
processor" idea. What was happening previously, was you had the
option of running DDR333 Command Rate 1T or DDR400 Command Rate 2T.
One poster here found by experiment, that the latter of those
two options is the better one, but just slightly.
Try running DDR400 Command Rate 2T, and use memtest86+ and Prime95
to test for correct operation.
The Command Rate 2T problem has existed for a long time, and is
not restricted to just the Athlon64. It has to do with what happens
when a large number of capacitive loads are placed on the
address/control bus. When a memory controller puts address/control
info on the bus, there is Tpd (time for signal to leave the
memory controller chip), time of flight down the bus, plus
the time to charge up all the memory chip inputs. The memory
needs a little advanced warning of the signal levels, and that
is called Tsetup. With Command Rate 1T timing, Tpd+Tsetup must
be less than one clock cycle, in order for the information to
"make it in time", before the memory clock triggers the sampling
of data.
How can you make it go faster ? You can use more powerful drivers,
subject to the tendency for impedance mismatch and ringing if you
do that. The biggest downside to such an approach, is it creates
more noise on the driving chip, requiring more power/ground pads
on the driving chip, to try to reduce the impact of simultaneous
switching (injection of error-creating noise onto the chip die).
Basically translated, at some point the chip designer is between
"a rock and a hard place". There really isn't room for significant
improvements in memory controller performance, despict the bullshit
you read on popular websites.
Now, why might an Intel solution achieve more than an AMD solution ?
On Intel motherboards right now, the memory controller is in a
separate chip from the processor. That means there are more power/gnd
pads to balance the needs of I/O drivers. The minus of that
approach is increased latency for the first cycle of data. The
plus is that there might be an opportunity to do a tiny bit
better at solving signal integrity issues.
In summary, if you are expecting a miracle when it comes to
driving DIMMs (like DDR400 Command Rate 1T with four DIMMs),
I don't see that happening. Perhaps when DDR2 comes along, things
will change. I really don't know enough about the I/O type
differences, to know how that changes things. But basically,
whatever characteristics are seen on the first of the Athlon64
DDR2 processors, will likely hound the design for the remainder
of its DDR2 lifetime. (I.e. Follow-on DDR2 processor designs will
do no better job of driving the memory bus, than the first DDR2
processor design.)
HTH,
Paul
