"John" said:
Ru HDtach and results come out ok,also have uninstalled disk controller
driver, but to no avail.
This may sound like a stupid question, but why is the cpu sold as having a
fsb of 1000mhz, but in the bios only shows to be a fsb of 200 mhz even
though the resulting system speed with multiplier is correct ??
To answer that, we need a block diagram of the Athlon64. This
AMD doc is the source of my figure below - page 8:
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/Hammer_architecture_WP_2.pdf
CPU_Core
|
SRQ (system_request_queue)
|
XBAR---MCT---DCT
^ | ^ ^
| | | |
16 / / 16 64 / / 64
| | | |
| v v v 8bytesxDDR400 per DIMM = 3.2GB/sec
Hypertransport Memory 6.4GB/sec total, two channels
Hypertransport ==> CLKx2(DDR)x#bits/8bits_per_byte
= 1000MHz x 2 x 16 / 8 = 4GB/sec (each direction)
CPU_clock x multiplier = CPU_core_clock 200 x 11 = 2200 (3500+)
CPU_clock x LDT_multiplier = HT_clock ex. 200 x 5 = 1000
CPU_core_clock / divider = Memory_clock 2200/11 = 200 (DDR400)
To see examples of divider choices used by the processor, see posting
#7 in this thread. (Oskar Wu designs DFI Athlon64 motherboards AFAIK.)
The divider is set according to the user's "target" DRAM speed.
http://xtremesystems.org/forums/showthread.php?t=41595&highlight=divider
If the BIOS is showing "200" for something, that is the setting of
the clock generator chip. The rest of the clocks are derived from
that clock signal, via the various multipliers and dividers.
I'm not sure the concept of front side bus (FSB) is that useful
here. You might consider the FSB to be the bus at the top of the
SRQ, but unless someone tells us the width and the speed, we'd
never know what it was. Because the Northbridge functions are
more distributed in this architecture, with memory control in
the processor, and video card interface on the chipset, the
traditional FSB concept is kind of fuzzy.
Just a guess,
Paul