Hi,
I downloaded the latest manual of this ASUS M/B and it clearly says
that these board has 4 memory sockets with a picture clearly showing
only 3 sockets... Ok, just a little error in the manual. But the
problem continues even in the bios... If you look at the devices
enumeration screen (POST sequence before OS boot) showing informations
such as IDE devices type, IRQ numbers for onboard peripherals, etc...
you have a line "DDR Dimm at rows X X" where the "X" ar the sockets
number I believe. In my dual channel setup, the line says "DDR Dimm at
rows 2 4" !! Knowing that there is no fourth socket, that's pretty
strange. So what's wrong with these 3 sockets setup. Can someone
explain how such M/B manage our precious memory modules ? Is one of
the sockets seen as a dual one by the chipset ? If so wich one ?
Thanks in advance for your explanations.
Aramys
Well, as Nvidia doesn't make datasheets for the chipset available
on their site, we can only guess as to how it works. This
press release says "three DIMMs" and "full speed", so it is not
like Asus just left one off because there wasn't room in the layout.
http://nvidia.com/object/IO_20020715_4484.html
The Nforce2 has two memory data busses and three memory address
busses. Each DIMM gets its own address bus. This scheme is what
helps make it possible to run at DDR400 rates with all three
DIMMs populated. The private address busses means signal quality
can be better than almost any other chipset available. (Address
signals are what typically limits the number of DIMMs that a
motherboard can drive. With unbuffered DIMMs, a double sided
DIMM presents 16 chip loads, which is a lot to drive.)
The only question is, why did they stop there ? What prevented
them from adding a fourth address bus ? The count of pins on the
bottom of the Northbridge would be an issue, and as packages
come in discrete pin increments, perhaps adding a fourth bus
would have meant moving to the next largest package for the
device. (About 1/4 to 1/3 of the signals on the bottom of
the chip carry power and ground, so when adding signals, there
is an additional power/ground "tax" to be paid as well.)
Multiple address busses have been used before, and will be
used again. The Athlon64 (single channel DDR memory bus)
for example, has one data bus and two address busses, to drive
three DIMMs. One DIMM slot gets its own address bus and the
other two DIMMs share an address bus. The single DIMM slot
would be a better candidate for heavy loading DIMMs as a result.
In the case of the Athlon64, the address busses are the 1's
complement of one another, and this helps balance the switching
noise caused by the address bus. Since only one DIMM is
chip_selected at a time, the DIMMs only pay attention to
one of the address busses at any given time, allowing the
other one to have upside down signals without harming
anything.
In the case of the Athlon64, a similar question could be
asked. Why aren't there four DIMM slots ? All it would have
needed is enough added control signals to handle an extra
two banks of memory. Two DIMMs could be driven with one
address bus, and two with the other address bus.
It is all rather mysterous.
I like to think the Athlon64 ended up with three DIMM slots,
so it would appear inferior to the FX-51/53's four DIMM
slots. It is a marketing thing. And the FX-51's and Opterons
are what pay the bills at AMD. (With Opteron being picked
up by so many computer companies, AMD will be around for a
while yet.)
As for the Nforce2, there is no marketing argument for the
three slot limit. Maybe there isn't enough drive to handle
an extra load on the data bus ? That is hard to believe.
HTH,
Paul
